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Abstract

Electronic clocks have predominately replaced the mechanical clocks. They are much reliable, accurate, maintenance free and portable. In general, there are two kinds of electronic clocks. They are analog clock and digital clock. But digital clocks are more common and independent of external source.  It would be needed the controlled devices and implementation of software for microcontroller control system because the hardware devices cannot do any desired task to execute. In this paper, the Spartan3an FPGA based digital clock is constructed with XC3S50an and its software program is written with VHDL language. Various types of digital clocks and modules are available in the market nowadays but this clock is different at least in the accurate time. To be controlling in FPGA is only the feature of the clock. The input frequency is taken from the 50 Hz clock frequency circuit. To show the time, 2x16 LCD is used. 

Demonstration Video

 

Tool required

Software:

  • Xilinx ISE 10.1i or above

Language:

  • VHDL

Hardware:

 

Block Diagram for Implementation of Digital Clock using Spartan3an FPGA Evaluation Kit



Block_Dgm_Digital_Clock

Pin Assignment with Spartan3an

LCD and Clock XC3S50-Pins

RS  P105
RW P104
E P103
D0 P102
D1 P101
D2 P99
D3 P98
D4 P96
D5 P93
D6 P92
D7 P91
CLK P57

 

Introduction:

TIME is such a fundamental concept that it is very difficult to define. To measure time is needed something that will repeat itself at regular intervals. The number of intervals counted gives a quantitative measure of the duration. The earliest references for the measurement of the time are the moon and sun. When the sun and the moon were not visible, it was impossible to know the exact time. So, clocks were developed to measure out the hours between checks with the sun and the moon. The process of measuring time has progressively become more accurate, and the devices more localized ever since. In our modern time, the time is predominately measured by mechanical, and recently by electronic clocks. All clocks measure time, but different clocks can have status or importance. Many centuries have been spent devising method for the determination and measurement of time. Historically, clocks and watches of all sorts lie at an important crossroads of science, technology and society. Changes in timekeeping technology have influenced the character of scientific observation, aided the development of other machine technologies and brought significant revisions in the way people think about and behave in time. In this paper, the more accurate clock using FPGA is presented.

Design Consideration for Implementation

In the software implementation process, initialization processing, LCD display processing, time adjustment processing and time signal processing are considered.

In this paper, the FPGA-based digital clock is mainly controlled by the clock pulse frequency. The clock pulse frequency can be generated by using the 50 MHz Crystal. Every one hour is indicated by Buzzer indicator.

Flowchart for Digital Clock Display



flow_char_Digital_Clock

Spartan3an FPGA Evaluation Board LCD Placement



SP3_Digital_Clock

Source Code

Digital Clock using Output Image

 Digital Clock using Output Image

 

Digital Clock using Output Image

 

Digital Clock using Output Image

 

Digital Clock using Output Image

 

Digital Clock using Output Image

VHDL Code for Digital Clock Display using LCD in Spartan3an FPGA Evaluation Kit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clock is
port (clk1 : in std_logic;
		rw: out std_logic;     ---read write control
		rs:out std_logic;      ----command data control
		en:out std_logic;   	  
		data:out std_logic_vector(7 downto 0)
      );
end clock;

architecture Behavioral of clock is

component bin_ascii 
    Port ( bin : in  STD_LOGIC_VECTOR (7 downto 0);
           ascii : out  STD_LOGIC_VECTOR (7 downto 0);
           ascii1 : out  STD_LOGIC_VECTOR (7 downto 0));
end component;
signal  seconds, minutes, hours :	std_logic_vector(7 downto 0);  
signal sec,min,hour : integer range 0 to 60 :=0;
signal count : integer :=1;
signal clk : std_logic :='0';
signal out0,out1,out2,out3,out4,out5 :	std_logic_vector(7 downto 0);

begin
seconds <= conv_std_logic_vector(sec,8);
minutes <= conv_std_logic_vector(min,8);
hours <= conv_std_logic_vector(hour,8);

 --clk generation.For 50 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 25000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;

process(clk)   --period of clk is 1 second.
begin

if(clk'event and clk='1') then
	sec <= sec+ 1;
	if(sec = 59) then
		sec<=0;
		min <= min + 1;
		if(min = 59) then
			hour <= hour + 1;
			min <= 0;
			if(hour = 23) then
				hour <= 0;
			end if;
		end if;
	end if;
end if;

end process;

p1: bin_ascii port map( seconds(7 downto 0), out0, out1);
p2: bin_ascii port map( minutes(7 downto 0), out2, out3);
p3: bin_ascii port map( hours(7 downto 0), out4, out5);

process(clk1)
variable x,y : integer := 0 ;
begin
rw<='0';
if clk1'event and clk1 = '1' then

	if x <= 160000 then
		x := x + 1;
	elsif x > 160000 then
		x := 0 ;
		if y < 43 then
			y := y + 1 ;
		else
			y := 0;
		end if;
	end if;
	
	case y is 			--	ascii code of data to be displayed
	  
		when 1=> 
			data<="00111000"; ---38	2 lines and 5x7 matrix  
			en<='1';
			rs<='0';
		when 2=>
			rs<='0';
			en<='0';
		when 3=>
			data<="00001100"; ---0C	Display on, cursor off
			en<='1';
			rs<='0';
		when 4=>
			rs<='0';
			en<='0';
		when 5=> 
			data<="00000001";   ---clear display
			en<='1'; 
			rs<='0';   
		when 6=> 
			rs<='0'; 
			en<='0';  
		when 7=>
			data<="00000110"; ---06 Inc cursor(shift right)
			en<='1'; 
			rs<='0';   
		when 8=>
			rs<='0';  
			en<='0';  
		when 9=>
			data<="10000000"; ---80 Force cursor to 1st line
			en<='1'; 
			rs<='0';   
		when 10=>
			rs<='0';  
			en<='0';  
--------------------------------------------------------------------
		when 11=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 12=> 
			rs<='1';  
			en<='0'; 
		when 13=> 
			data<=out5;   	-- hr
			en<='1'; 
			rs<='1';   
		when 14=> 
			rs<='1';  
			en<='0';  
		when 15=> 
			data<=out4;    --hr 
			en<='1'; 
			rs<='1';   
		when 16=> 
			rs<='1';  
			en<='0';  
		when 17=> 
			data<="00111010";   	-- :
			en<='1'; 
			rs<='1';   
		when 18=> 
			rs<='1';  
			en<='0';  
		when 19=> 
			data<=out3;		-- min
			en<='1'; 
			rs<='1';  
		when 20=> 
			rs<='1';  
			en<='0';  
		when 21=> 
			data<=out2;    -- min
			en<='1'; 
			rs<='1';   
		when 22=> 
			rs<='1';  
			en<='0';  
		when 23=> 
			data<="00111010"; -- :
			rs<='1';  
			en<='1'; 
		when 24=> 
			rs<='1';  
			en<='0'; 
		when 25=> 
			data<=out1;    -- sec
			rs<='1';  
			en<='1'; 
		when 26=> 
			rs<='1';  
			en<='0'; 
		when 27=> 
			data<=out0;    -- sec
			rs<='1';  
			en<='1'; 
		when 28=> 
			rs<='1';  
			en<='0'; 			
		when 29=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 30=> 
			rs<='1';  
			en<='0';
		when 31=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 32=> 
			rs<='1';  
			en<='0';		
		when 33=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 34=> 
			rs<='1';  
			en<='0';
		when 35=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 36=> 
			rs<='1';  
			en<='0';
		when 37=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 38=> 
			rs<='1';  
			en<='0';		
		when 39=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 40=> 
			rs<='1';  
			en<='0';
		when 41=> 
			data<="00100000";    -- SPACE
			en<='1'; 
			rs<='1';   
		when 42=> 
			rs<='1';  
			en<='0';
----------------------------------------------------------------- 
		when others=> 
			data<="01000100";     --  ascii code for " " 
			rs<='1';  
			en<='0'; 
	end case; 
end if;
end process;

end Behavioral;

Binary_ascii.vhd

library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;

entity bin_ascii is
    port ( bin  : in  std_logic_vector (7 downto 0) ;
           ascii : out std_logic_vector (7 downto 0) ;
           ascii1 : out std_logic_vector (7 downto 0)  ) ;
end bin_ascii ;

architecture bhv of bin_ascii is
begin
process ( bin )
    variable hex_src : std_logic_vector (7 downto 0) ;
    variable bcd     : std_logic_vector (11 downto 0) ;
begin
    hex_src := bin ;
    bcd     := (others => '0') ;

    for i in 0 to 7 loop
        if bcd(3 downto 0) > "0100" then
            bcd(3 downto 0) := bcd(3 downto 0) + "0011" ;
        end if ;
        if bcd(7 downto 4) > "0100" then
            bcd(7 downto 4) := bcd(7 downto 4) + "0011" ;
        end if ;
        if bcd(11 downto 8) > "0100" then
            bcd(11 downto 8) := bcd(11 downto 8) + "0011" ;
        end if ;

        bcd := bcd(10 downto 0) & hex_src(7) ; -- shift bcd + 1 new entry
        hex_src := hex_src(6 downto 0) & '0' ; -- shift src + pad with 0
    end loop ;

    ascii1 <= "0011" & bcd(7  downto 4);
    ascii <= "0011" & bcd(3  downto 0);

end process ;
end bhv ;

Pin Assignment

NET "data[0]" LOC = P102;
NET "data[1]" LOC = P101;
NET "data[2]" LOC = P99;
NET "data[3]" LOC = P98;
NET "data[4]" LOC = P96;
NET "data[5]" LOC = P93;
NET "data[6]" LOC = P92;
NET "data[7]" LOC = P91;
NET "clk1" LOC = P57;
NET "en" LOC = P103;
NET "rs" LOC = P105;
NET "rw" LOC = P104;

Conclusion

The Spartan3an FPGA Evaluation Kit based digital clock is mainly controlled by the clock pulse frequency. The clock pulse frequency can be generated by using the 50 MHz Crystal.  Every one hour is indicated by Buzzer indicator.