VGA interface with Cyclone FPGA Development Kit
VGA interface with Cyclone FPGA Development Kit
VGA
The following table describes pin details of DB15 VGA Connector
The following table describes the color production by 3-bit VGA monitor Signals.
The following table describes the color production by 3-bit VGA monitor Signals.| RED | GREEN | BLUE | RESULTING COLOUR |
| 0 | 0 | 0 | BLACK |
| 0 | 0 | 1 | BLUE |
| 0 | 1 | 0 | GREEN |
| 0 | 1 | 1 | CYAN |
| 1 | 0 | 0 | RED |
| 1 | 0 | 1 | MAGNETA |
| 1 | 1 | 0 | YELLOW |
| 1 | 1 | 1 | WHITE |
Interfacing VGA with Cyclone FPGA Development Kit
VGA interface with FPGA is performed by placing 270 OHM Resister value serial to FPGA pin R, G, B. The Remaining 2 pins, Horizontal Sync and Vertical Sync taking care of timing of scan rate.
Horizontal Sync performs controlling operation for start and end of line pixel is displaying on the visible area of the monitor. Similarly Vertical Sync performs controlling operation for Start and End of Frame is displaying on the top and bottom visible area of the monitor. 
VGA Connector Placement in Cyclone FPGA Development Kit
To get the pixel resolution of 640×480, 50 MHz needs to be divided by 2. The Output 25 MHz clock frequency is required to perform the VGA Control Operation.
VHDL Code description for VGA Interface
The following VHDL code for VGA interface with Cyclone3 FPGA Development Kit, displays pixel value in VGA Monitor at 25 MHz Clock frequency. Graphical output display PANTECH SOLUTIONS in RED color.
VHDL Code for VGA Display
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity VGA is
port(clk50_in : in std_logic; -----system clock i/p
red : out std_logic; -----primrary colour output
green : out std_logic;
blue : out std_logic;
hs_out : out std_logic; ------horizontal control signal
vs_out : out std_logic); ------vertical control signal
end VGA;
architecture Behavioral of VGA is
signal clk25 : std_logic;
signal hs : std_logic_vector (9 downto 0);
signal vs : std_logic_vector (9 downto 0);
begin
-- generate a 25Mhz clock
process (clk50_in)
begin
if clk50_in'event and clk50_in='1' then
if (clk25 = '0') then
clk25 <= '1';
else
clk25 <= '0';
end if;
end if;
end process;
------display logic for message "PANTECH SOLUTIONS"
process (clk25)
begin
if clk25'event and clk25 = '1' then
if hs = "0011001000" and vs >= "0011001000" and vs <= "0011111010" then ---horizantal and vertical line display constraint
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0011001000" and vs >= "0100101100" and vs <= "0101000101" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0011111010" and vs >= "0011001000" and vs <= "0011100001" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0011111010" and vs >= "0101000101" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0100000100" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0100000100" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0100110110" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0100110110" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0101000000" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0101000000" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0101110010" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0101111110" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0110101110" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0110010101" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0110111000" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0111010001" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "0111110100" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1000001101" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1000110000" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1001100010" and vs >= "0011001000" and vs <= "0011111010" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1000110000" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1001100010" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1001101100" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
elsif hs = "1010011110" and vs >= "0100101100" and vs <= "0101011110" then
red <= '1' ;
blue <= '0';
green <= '0' ;
--------------------------------------------------------------------------------
else ----------blank signal display
red <= '0' ;
blue <= '0';
green <= '0' ;
end if;
if (hs > "0000000000" )
and (hs < "0001100001" ) -- 96+1 -----horizontal tracing
then
hs_out <= '0';
else
hs_out <= '1';
end if;
if (vs > "0000000000" )
and (vs < "0000000011" ) -- 2+1 ------vertical tracing
then
vs_out <= '0';
else
vs_out <= '1';
end if;
hs <= hs + "0000000001" ;
if (hs= "1100100000") then ----incremental of horizontal line
vs <= vs + "0000000001"; ----incremental of vertical line
hs <= "0000000000";
end if;
if (vs= "1000001001") then
vs <= "0000000000";
end if;
end if;
end process;
end Behavioral;
User Constraint File
NET "blue" LOC = "p26" ; NET "clk50_in" LOC = "p181" ; NET "green" LOC = "p24" ; NET "hs_out" LOC = "p21" ; NET "red" LOC = "p27" ; NET "vs_out" LOC = "p22"
