TMS320C6745 DSP Evaluation Board
₹26,500.00 Exc Tax
Key Features of TMS320C6745 DSP Evaluation Board
- 256K bytes on-chip RAM.
- On Board 16M bytes on-chip SDRAM Memory.
- Boot ROM (8K x 16) via SCI.
- On Board XDS100 Emulator for Execution,IEEE 1149.1 JTAG emulation connector,25 MHz crystals
- Motor Control Peripherals.
- Serial Communications Interfaces (SCIs), UART
- On Board 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface.
- Up to 109 individually Programmable, Multiplexed General-Purpose Input/output (GPIO) Pins.
- 12 Digital LED Outputs and 8 Digital Inputs.
- Multiple Booting Option DIP Switches.
- On Board Reset Switch.
Shipping : 4 to 8 days from the Date of purchase
Warranty : 1 year against Manufacturing defects
Support : Email / Phone / Chat / Online Resources
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The C6745 DSP Evaluation Board is a Low-power digital signal processor based on C674x DSP core. It consumes significantly lower power than other members of the TMS320C6000™ Platform of DSP’s. The C6745/6747 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM.
The C6745 DSP Evaluation Board is highly integrated, high-performance solution for demanding control applications and is the first 32-bit 150 MIPS DSP.
Benefits of TMS320C6745 DSP Evaluation Board
- 300 MHz (6.67-ns Cycle Time).
- Fixed/Floating Point Processor.
- Advanced Motor control.
- Commercial, Industrial or Automotive Temperature.
- Signal Processing Applications.
- Servo drives and motion control.
TEXAS – TMS320C6745
- Two Serial Peripheral Interfaces (SPI)
- C674x Two Level Cache Memory Architecture
- 256K-Byte L2 Unified Mapped RAM/Cache.
- 1024K-Byte L2 ROM.
DSP Kit Includes
- TMS320C6745 DSP Evaluation Board
- 5V Power Adaptor.
- RS232 Serial Cable.
- USB Cable.
- CD Contains: