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DC Motor Interface with FPGA

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DC Motor

A DC motor is an electric motor that runs on direct current (DC) electricity. DC motors were used to run machinery, often eliminating the need for a local steam engine or internal combustion engine.

A direct current (DC) motor is another widely used device that translates electrical pulses into mechanical movement. In the DC motor we have only + and – leads. Connecting them to a DC voltage source moves the motor in one direction. By reversing the polarity, the DC motor will move in the opposite direction. One can easily experiment with the DC motor. For example, small fans used in many motherboards to cool the CPU are run by DC motors. By connecting their leads to the + and – voltage source, the DC motor moves. While a stepper motor moves in steps of 1 to 15 degrees, the DC motor moves continuously. In a stepper motor, if we know the starting position we can easily count the number of steps the motor has moved and calculate the final position of the motor. This is not possible in a DC motor.

Interfacing DC Motor with FPGA Development Kit

The Spartan3 FPGA Development Kit has external DC motor interfacing, indicated as in Figure. 5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program.

Schematics to Interface DC Motor with FPGA Development Kit

DC Motor Driver IC Placement in FPGA Development Kit

VHDL Code Description

The following DC Motor Code generates PWM pulse to run DC motor. To run the motor in Counter Clockwise direction invert output1 to LOW and Output2 to HIGH.

VHDL Program for DC Motor using FPGA Development Kit

           library IEEE;         
            use IEEE.STD_LOGIC_1164.ALL;         
            use IEEE.STD_LOGIC_ARITH.ALL;         
            entity first is
            port ( clk : in std_logic;
                   rst : in std_logic;

                           enable : out std_logic;
                           output1 : out std_logic;
                           output2 : out std_logic);

            end first;
            architecture Behavioral of first is
            variable i : integer := 0;
            if rst = '1' then
            if clk'event and clk = '1'  then
            enable <= '1';
            if i <= 1005000 then
            i := i + 1;
            output1 <= '0';
            output2 <= '0';
            elsif i > 1005000 and i < 1550000 then
            i := i + 1;
            output1 <= '1';
            output2 <= '0';
            elsif i = 1550000 then
            i := 0;
            end if;

            end if;
            end if;
            end process;
            end Behavioral;

User Constraint File

NET "clk" LOC = P181;

NET "enable" LOC = P19;

NET "output1" LOC = P22;

NET "output2" LOC = P20;

NET "rst" LOC = P46;

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