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VHDL Code for PWM Generation Using FPGA

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DC Motor (To controlled speed of DC Motor using PWM)

Description

In this example to rotate DC motor clockwise/counter clockwise continuously the motor interface card. For that in Spartan3 FPGA lines (P77, P78) are configured for (Coil-A to Coil-B). FPGA Lines (P79) to enable the dc motor. User could verify the result by β€œStepper/DC motor Card” connected to the PGASP3 KIT at connector J6.

Flow Chart

Interfacing DC Motor with FPGA Development Kit

The FPGA Development Kit has external DC motor interfacing, indicated as in Figure. 5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program.

Schematics to Interface DC Motor with FPGA Development Kit

DC Motor Driver IC Placement in FPGA Development Kit

VHDL Code Description

The following DC Motor Code generates PWM pulse to run DC motor. To run the motor in Counter Clockwise direction invert output1 to LOW and Output2 to HIGH.

VHDL Program for DC Motor using FPGA Development Kit

           library IEEE;         
            use IEEE.STD_LOGIC_1164.ALL;         
            use IEEE.STD_LOGIC_ARITH.ALL;         
            use IEEE.STD_LOGIC_UNSIGNED.ALL;
        
            entity first is
        
            port ( clk : in std_logic;
        
                   rst : in std_logic;
        

                           enable : out std_logic;
        
                           output1 : out std_logic;
        
                           output2 : out std_logic);
        

            end first;
                
            architecture Behavioral of first is
        
            begin
        
            process(rst,clk)
        
            variable i : integer := 0;
        
            begin
        
            if rst = '1' then
        
            if clk'event and clk = '1'  then
        
            enable <= '1';
        
            if i <= 1005000 then
        
            i := i + 1;
        
            output1 <= '0';
        
            output2 <= '0';
        
            elsif i > 1005000 and i < 1550000 then
        
            i := i + 1;
        
            output1 <= '1';
        
            output2 <= '0';
        
            elsif i = 1550000 then
        
            i := 0;
        
            end if;
        

            end if;
        
            end if;
        
            end process;
        
            end Behavioral;

User Constraint File

NET "clk" LOC = P181;

NET "enable" LOC = P19;

NET "output1" LOC = P22;

NET "output2" LOC = P20;

NET "rst" LOC = P46;

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