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Abstract

This Project implements FPGA based patient monitoring system using Medical Alert Bracelets offers an empowering option for individuals affected with chronic illnesses or medical conditions who may present more frequently to the ER. Trying to identify an unconscious patient or patient who is unable to communicate can lead to delays in treatment. With Medical Alert Bracelets emergency departments improve efficiency while enhancing the level of patient care. If you have a medical condition such as a life threatening food or medicine allergy, a pre-existing medical condition or maybe even a rare blood type, a medical alert bracelet may be the only communication you have to let emergency medical staff know so they can provide the proper treatment for you without potentially doing more harm. RF Transmitter is used as Medical alert Bracelet. Receiver section is equipped with Spartan3an FPGA Starter Kit and RF Receiver TAG.

demonstration Video

 

Tool required

Software:

  • Xilinx ISE 11.1i
  • Language: VHDL

Hardware:

Block Diagram for Patient Monitoring using Spartan3an FPGA Starter Kit

Reader and PC section



Person Section:


Person_Section

Introduction:

RFID in Healthcare

The term radio frequency identification (RFID) describes a wireless identification technology that communicates data by using radio waves. RFID is now generating significant interest in the marketplace because of its robust application capabilities. Thus, RFID can provide a number of benefits to the healthcare industry, improving overall safety and operational efficiency because it operates without line-of-sight while providing read/write capabilities.

RF Module

The RF module, as the name suggests, operates at Radio Frequency. The corresponding frequency range varies between 30 kHz & 300 GHz. In this RF system, the digital data is represented as variations in the amplitude of carrier wave. This kind of modulation is known as Amplitude Shift Keying (ASK).

Interfacing RF Module with Spartan3an FPGA Starter Kit

The Spartan-3an board has external RF Module interfacing, indicated as in Figure 4. This RF module comprises of an RF Transmitter and an RF Receiver. The transmitter/ receiver (Tx/Rx) pair operates at a frequency of 434 MHz. An RF transmitter receives serial data and transmits it wirelessly through RF through its antenna connected at pin4 at the rate of 1Kbps - 10Kbps. The transmitted data is received by an RF receiver operating at the same frequency as that of the transmitter. The encoder is used for encoding parallel data for transmission feed while reception is decoded by a decoder. Finally connected with FPGA I/O lines.



Figure 1: RF Transmitter and Reciever

RF Transmitter Pin Description

Pin No

Description

1

Ground

2

Data

3

Power Supply

4

Antenna

RF Receiver Pin Description

RF EncoderRF transmitter consists of RF Encoder HT12E IC. It performs Parallel to Serial conversion. HT12E IC encodes 12 bit of Address and Data to RF Transmitter for serial transmission.

RF_Encoder

Figure 2: RF Encoder HC12E ICRF DecoderRF receiver consists of RF Decoder HT12D IC. It performs Serial to Parallel conversion. HT12D IC decodes 12 bit of Address and Data from RF receiver for parallel reception.

Patient monitoring output image

Patient monitoring output image

 

 Patient monitoring output image

 

 Patient monitoring output image


 Patient monitoring output image
Source Code

VHDL Code for patient monitoring System using Spartan3an FPGA Starter Kit

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity patient_monitor is

port(clock:in std_logic;

		d0,d1,d2,d3:in std_logic;

   led:out std_logic;

rw: out std_logic;

rs:out std_logic;

en:out std_logic;

data:out std_logic_vector(7 downto 0));

end patient_monitor;

 

architecture arch of patient_monitor is

signal clkout:std_logic:='0';

type state is(state1,state2,state3,state4,state5,state6,state7,state8,

state9,state10,state111,state11,state12,state13,state14,

state15,state16,state17,state18,state19,state110,state121);

  signal current_state,next_state:state;

  signal count:integer:=0;

begin

process(clock)

begin

if clock'event and clock='1' then

 

count<=count + 1;          --  count for delay

 

if count =500000 then

clkout<= not clkout;

count<=0;

   end if;

end if;

end process;

led<=clkout;

process(clkout)

begin

if clkout'event and clkout='1' then

     current_state<=next_state;

end if;

end process;

 

process(current_state,next_state)

begin

 

en<='1';

rw<='0';

if (d0&d1&d2&d3="1111")then

case current_state is

when state1=>

data<="00111000";

en<='1'; rs<='0'; rw<='0';

next_state<=state11;

when state11=>

rs<='0'; rw<='0'; en<='0';

next_state<=state2;

when state2=>

data<="00001110";

en<='1'; rs<='0'; rw<='0';

next_state<=state12;

when state12=>

rs<='0'; rw<='0'; en<='0';

next_state<=state3;

when state3=>

data<="00000001";

en<='1'; rs<='0'; rw<='0';

next_state<=state13;

when state13=>

rs<='0'; rw<='0'; en<='0';

next_state<=state4;

when state4=>

data<="00000110";

en<='1'; rs<='0'; rw<='0';

next_state<=state14;

when state14=>

rs<='0'; rw<='0'; en<='0';

next_state<=state5;

when state5=>

data<="10000000";

en<='1'; rs<='0'; rw<='0';

next_state<=state15;

when state15=>

rs<='0'; rw<='0'; en<='0';

next_state<=state6;

when state6=>

data<="00110001";    --  ascii code for "H"

en<='1'; rs<='1'; rw<='0';

 

next_state<=state16;

when state16=>

rs<='1'; rw<='0'; en<='0';

next_state<=state7;

when state7=>

data<="00110000";    --  ascii code for "E"

en<='1'; rs<='1'; rw<='0';

next_state<=state17;

when state17=>

 

rs<='1'; rw<='0'; en<='0';

next_state<=state9;

when state9=>

data<="00110000";         --  ascii code for "L"

en<='1'; rs<='1'; rw<='0';

next_state<=state19;

when state19=>

rs<='1'; rw<='0'; en<='0';

next_state<=state10;

when state10=>

data<="00110000";         --  ascii code for "L"

en<='1'; rs<='1'; rw<='0';

next_state<=state110;

when state110=>

rs<='1'; rw<='0'; en<='0';

next_state<=state111;

when state111=>

data<="00110000";         --  ascii code for "O"

en<='1'; rs<='1'; rw<='0';

next_state<=state121;

when state121=>

rs<='1'; rw<='0'; en<='0';

next_state<=state8;

 

when state8=>

      next_state<=state8;

when others=>

       next_state<=state8;

end case;

 

else

case current_state is

when state1=>

data<="00111000";

en<='1'; rs<='0'; rw<='0';

next_state<=state11;

when state11=>

rs<='0'; rw<='0'; en<='0';

next_state<=state2;

when state2=>

data<="00001110";

en<='1'; rs<='0'; rw<='0';

next_state<=state12;

when state12=>

rs<='0'; rw<='0'; en<='0';

next_state<=state3;

when state3=>

data<="00000001";

en<='1'; rs<='0'; rw<='0';

next_state<=state13;

when state13=>

rs<='0'; rw<='0'; en<='0';

next_state<=state4;

when state4=>

data<="00000110";

en<='1'; rs<='0'; rw<='0';

next_state<=state14;

when state14=>

rs<='0'; rw<='0'; en<='0';

next_state<=state5;

when state5=>

data<="10000000";

en<='1'; rs<='0'; rw<='0';

next_state<=state15;

when state15=>

rs<='0'; rw<='0'; en<='0';

next_state<=state6;

when state6=>

data<="00110000";    --  ascii code for "H"

en<='1'; rs<='1'; rw<='0';

next_state<=state16;

when state16=>

rs<='1'; rw<='0'; en<='0';

next_state<=state7;

when state7=>

data<="00110000";    --  ascii code for "E"

en<='1'; rs<='1'; rw<='0';

next_state<=state17;

when state17=>

rs<='1'; rw<='0'; en<='0';

next_state<=state9;

when state9=>

data<="00110000";         --  ascii code for "L"

en<='1'; rs<='1'; rw<='0';

next_state<=state19;

when state19=>

rs<='1'; rw<='0'; en<='0';

next_state<=state10;

when state10=>

data<="00110000";         --  ascii code for "L"

en<='1'; rs<='1'; rw<='0';

next_state<=state110;

when state110=>

rs<='1'; rw<='0'; en<='0';

next_state<=state111;

when state111=>

data<="00110001";         --  ascii code for "O"

en<='1'; rs<='1'; rw<='0';

next_state<=state121;

when state121=>

rs<='1'; rw<='0'; en<='0';

next_state<=state8;

 

when state8=>

      next_state<=state8;

when others=>

       next_state<=state8;

end case;

end if;

end process;

end arch;


ConclusionProposed System is implemented in Spartan3an FPGA Starter Kit and output is transferred through RS232 and monitored in PC with VB GUI.

Pin No

Description

1

Ground

2

Data

3

No connect

4

Power Supply

5

Power Supply

6

Ground

7

Ground

8

Antenna