VHDL code to simulate 4-Bit Binary Counter by software using spartan 3 Starter Kit

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VHDL code to simulate 4-bit Binary Counter by Software

SKU: VHDL code to simulate 4-bit Binar Category:

Description

VHDL code to simulate 4-bit Binary Counter by Software

Experiments Covered

☞Up Counter

☞Down Counter

☞Up/Down Counter

Software – Xilinx ISE 9.2

VHDL code to simulate 4-Bit Binary Counter by software

COUNTERS

A counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. There are two types of counters:

☞up counters

☞down counters

Up counters

Each of the higher-order flip-flops are made ready to toggle (both J and K inputs “high”) if the Q outputs of all previous flip-flops are “high.” Otherwise, the J and K inputs for that flip-flop will both be “low,” placing it into the “latch” mode where it will maintain its present output state at the next clock pulse. Since the first (LSB) flip-flop needs to toggle at every clock pulse, its J and K inputs are connected to Vcc or Vdd, where they will be “high” all the time.

Up Counter (Program for 4-bit binary counter using behavior description)

Description

In this program an up counter has a 1- bit input and a 4- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.

Flow Chart

vhdl-up-counter-flow-chart-of-tyro

Code Listing

   library IEEE;
        
            use ieee.std_logic_1164.all;
        
            use ieee.std_logic_unsigned.all;
        
            entity counter is 
        
             port(Clock, CLR : in  std_logic;
        
             Q : out std_logic_vector(3 downto 0));
        
             end counter;
        
             architecture archi of counter is  
        
             signal tmp: std_logic_vector(3 downto 0);
        
             begin
        
             process (Clock, CLR) 
        
             begin   
        
                   if (CLR='1') then   
        
                          tmp <= "0000";  
        
                   elsif (Clock'event and Clock='1') then 
        
                          tmp <= tmp + 1;
        
                   end if;     
        
             end process; 
        
                   Q <= tmp;
        
             end archi;
			 

Result

SW : PSTYRO-FPGASP3\Code\EXA-8a\…………..

up-counter

Down Counter (Program for 4-bit binary counter using behavior description)

Description

In this program a down counter has a 1- bit input and a 4- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.

Flow Chart

vhcl-down-counter-flow-chart-of-tyro

Code Listing

   library IEEE;
        
            use ieee.std_logic_1164.all;
        
            use ieee.std_logic_unsigned.all;
        
            entity counter is 
        
             port(Clock, CLR : in  std_logic;
        
             Q : out std_logic_vector(3 downto 0));
        
             end counter;
        
             architecture archi of counter is  
        
             signal tmp: std_logic_vector(3 downto 0);
        
             begin
        
             process (Clock, CLR) 
        
             begin   
        
                   if (CLR='1') then   
        
                          tmp <= "0000";  
        
                   elsif (Clock'event and Clock='1') then 
        
                          tmp <= tmp + 1;
        
                   end if;     
        
             end process; 
        
                   Q <= tmp;
        
             end archi;
 


Result


SW : PSTYRO-FPGASP3\Code\EXA-8a\..............




up-counter


Down Counter (Program for 4-bit binary counter using behavior description)


Description


In this program a down counter has a 1- bit input and a 4- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.


Flow Chart




vhcl-down-counter-flow-chart-of-tyro


Code Listing


 


            library ieee;
        
            use ieee.std_logic_1164.all;
        
            use ieee.std_logic_unsigned.all;
        
            entity counter is 
        
             port(Clock, CLR : in  std_logic;
        
             Q : out std_logic_vector(3 downto 0));
        
             end counter;
        
             architecture archi of counter is  
        
             signal tmp: std_logic_vector(3 downto 0);
        

             begin
        
             process (Clock, CLR) 
        
             begin   
        
                   if (CLR='1') then   
        
                          tmp <= "1111";  
        
                   elsif (Clock'event and Clock='1') then 
        
                          tmp <= tmp - 1;
        
                   end if;     
        
             end process; 
        
                   Q <= tmp;
        

             end archi;
        
             end process; 
        
                   Q <= tmp;
        
             end archi;
			 

Result

SW : PSTYRO-FPGASP3\Code\EXA-8b\…………..

down-counter

Up/Down Counter (Program for 4-bit binary counter using behavior description)

Description

The Up/Down control input line simply enables either the upper string or lower string of AND gates to pass the Q/Q’ outputs to the succeeding stages of flip-flops. If the Up/Down control line is “high,” the top AND gates become enabled. If the Up/Down control line is made “low,” the bottom AND gates become enabled.

Flow Chart

up-down-counter-flow-chart-of-tyro

Code Listing

            library ieee;
        
                   use ieee.std_logic_1164.all;
        
                   use ieee.std_logic_unsigned.all;
        
            entity counter is  
        
            port(C, CLR, up_down : in std_logic;
        
                    Q : out std_logic_vector(3 downto 0));
        
                            end counter;
        
            architecture archi of counter is 
        
             signal tmp: std_logic_vector(3 downto 0);  
        
             begin     
        
             process (C, CLR)   
        
             begin       
        
             if (CLR='1') then         
        

             tmp <= "0000";        
        
             elsif (C'event and C='1') then  
        
             if (up_down='1') then  
        

             tmp <= tmp + 1;        
        

             else           
        
             tmp <= tmp - 1;    
        

             end if;        
        
             end if;  
        
             end process;   
        
             Q <= tmp;
        
             end archi;
        
             end process; 
        
                  Q <= tmp;
        
             end archi;
        
              end process; 
        
                  Q <= tmp;
        
             end archi;
			 

up-down-counter

Additional information

Weight 0.100000 kg

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