VGA Based Bouncing Ball interface using Spartan3 FPGA Image Processing Kit
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In this project, we present the design and implementation of efficient hardware architecture for VGA monitor controllers based on Spartan3 FPGA Image Processing kit.
Features:
VGA interfacing with fpga processor
Shipping : 2 to 5 working days from the Date of purchase
Package Includes:
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Complete Hardware Kit
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Demo Video-Embedded Below
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Abstract
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Reference Paper
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Description
Abstract
In this project, we present the design and implementation of efficient hardware architecture for VGA monitor controllers based on Spartan3 FPGA Image Processing Kit. The design implement the bouncing ball in the VGA monitor using VHDL Code The ability to provide multiple display resolutions (up to WXGA 1280× 800) and a customizable internal FIFO make the proposed architecture suitable for several FPGA devices. The output of the display produce bouncing ball with different colour making contact at the four sides of the monitor.
Demonstration Video
Tool required
Software:
- Xilinx ISE 10.1i or above
Language:
- VHDL
Hardware:
- Spartan3 FPGA Image Processing Kit
- JTAG Cable
- Monitor
Block Diagram for VGA Based Bouncing Ball interface using Spartan3 FPGA Image Processing Kit
Introduction
VGA display port through DB15 connector, Connect this port directly to most PC monitors or flat-panel LCD displays using a standard monitor cable As shown in table, VGA signals: RED (R) its 1ST pin in connector, GREEN (G) its 2nd pin, BLUE (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all available on the VGA connector. The standard VGA monitor consists of 640×480 pixel values. To display image in the LCD Monitor, pixel values need to be continuously on/off at certain frame rate.
The following table describes pin details of DB15 VGA Connector
The following table describes the color production by 3-bit VGA monitor Signals.
Interfacing VGA with Spartan3 FPGA Development Kit
VGA interface with FPGA is performed by placing 270 OHM Resister value serial to FPGA pin R, G, B. The Remaining 2 pins, Horizontal Sync and Vertical Sync taking care of timing of scan rate. Horizontal Sync performs controlling operation for start and end of line pixel is displaying on the visible area of the monitor. Similarly Vertical Sync performs controlling operation for Start and End of Frame is displaying on the top and bottom visible area of the monitor.
Bouncing Ball Output Image
Conclusion
As a result of implementation, the output of the display produce bouncing ball with different colour making contact at the four sides of the monitor. Able to meet different requirements of targeted applications.
Additional information
Weight | 1.000000 kg |
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