User Manual for Spartan3 FPGA Image Processing Board

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User Manual for Spartan3 FPGA Image Processing Board

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Description

Spartan3 FPGA Image Processing Board

Introduction

The Spartan3 FPGA Image Processing Board provides a powerful, self-contained development platform for designs targeting the new Spartan-3 FPGA from Xilinx. It features a 200K gate SPARTAN-3, on-board I/O devices, and 1MB fast asynchronous SRAM, making it the perfect platform to experiment with any new design, from a simple logic circuit to an embedded processor core. The board also contains a Platform Flash JTAG-programmable ROM, so designs can easily be made non-volatile. The spartan starter board is fully compatible with all versions of the Xilinx ISE tools, including the free Web Pack. The board ships with a power supply, and a programming cable.

Package Contents

Xilinx Spartan3 XC3S200 FPGA Kit

☞Serial Port Cable (DTE)

JTAG Download Cable

☞Printed User Manual

☞5V Power AC Adaptor

LCD module

☞CD contains a) Software b) Example Programs c) User Manual d) Simple Projects

Learning Xilinx FPGA and ISE Development Software Basics

The Spartan-3 EDK Board provides a powerful, self-contained development platform for designs targeting the new Spartan-3 FPGA from Xilinx. It features a 200K gate SPARTAN-3, on-board I/O devices, and 1MB fast asynchronous SRAM, making it the perfect platform to experiment with any new design, from a simple logic circuit to an embedded processor core. The board also contains a Platform Flash JTAG-programmable ROM, so designs can easily be made non-volatile.

Components placement

tyro-plus-spartan3-edk-board

Figure 1. PS – TYRO PLUS SPARTAN3 (EDK) Board Components placement top view

Block Diagram

xilinx-spartan3advanced-development-board

Figure 2. Xilinx Spartan3Advanced Development Board Block Diagram

Power Distribution

AC Wall Adapter

The Spartan3FPGA Lab Kit includes an international-ready AC wall adapter that produces a +5V DC output. Connect the AC wall adapter to the barrel connector along the left edge of the board, indicated as in Figure 3. To disconnect power, switch off the power switch. The power indicator LED, as shown in Figure 3, lights up when power is properly applied to the board. The AC wall adapter operates from 100V to 240V AC input, at 50 or 60 Hz.

Voltage Regulators

There are Overall, the 5V DC switching power adapter that connects to AC wall power powers the board. A 3.3V regulator, powered by the 5V DC supply, provides power to the inputs of the 2.5V and 1.2V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The VCCAUX voltage input supplies power to Digital Clock Managers (DCMs) within the FPGA and supplies some of the I/O structures. In specific, all of the FPGA’s dedicated configuration pins, such as DONE, PROG_B, CCLK, and the FPGA’s JTAG pins, are powered by VCCAUX. The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic. The board uses three discrete regulators to generate the necessary oltages. However, various power supply vendors are developing integrated solutions specifically for Spartan-3 FPGA.

power-supply-tyro-plus

Figure 3. Power Supply

On-board Peripherals

The Spartan3FPGA Lab Kit comes with many interfacing options

☞2 Nos. of Seven-segment display

☞8-Nos. of Toggle switches (Digital Inputs)

☞4-Nos. of Push Button (Digital Inputs)

☞8-Nos. of Point LED’s (Digital Outputs)

☞2×16 Character LCD

UART for serial port communication through PC

PS/2 keyboard Interface

☞3-Bit VGA Interface

Seven Segment Display

The Spartan3 FPGA Kit has a two-character, seven-segment LED display controlled by FPGA user-I/O pins, as shown in Figure 4. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each FPGA pin connected to the LED display is shown in Table 1. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.

seven-segment-display--tyro-plus

Figure 4. Seven-segment display connections from Spartan3FPGA Lab Kit

Table 1. Seven-segment display connections to the FPGA pins

 

Segment

FPGA PIN

A

P82

B

P83

C

P84

D

P85

E

P86

F

P87

G

P89

DP

P90

 

Table 2. Digit Enable (Anode Control) Signals (Active Low)

Anode Control

FPGA PIN

AN1

P76

AN0

P77

 

The LED control signals are time-multiplexed to display data on two characters. Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low. Through persistence of vision, the human brain perceives that all four characters appear simultaneously, similar to the way the brain perceives a TV display.

This “scanning” technique reduces the number of I/O pins required for the four characters. In case an FPGA pin were dedicated for each individual segment, then 32 pins are required to drive four 7-segment LED characters. The scanning technique reduces the required I/O down to 12 pins. The drawback to this approach is that the FPGA logic must continuously scan data out to the displays—a small price to save 20 additional I/O pins.

Table 3. Display Characters and Resulting LED Segment Control Values

 

Character

a

b

c

d

e

f

g

1

1

0

0

1

1

1

1

2

0

0

1

0

0

1

0

3

0

0

0

0

1

1

0

4

1

0

0

1

1

0

0

5

0

1

0

0

1

0

0

6

0

1

0

0

0

0

0

7

0

0

0

1

1

1

1

8

0

0

0

0

0

0

0

9

0

0

0

0

1

0

0

A

0

0

0

1

0

0

0

B

1

1

0

0

0

0

0

C

0

1

1

0

0

0

1

D

1

0

0

0

0

1

0

E

0

1

1

0

0

0

0

F

0

1

1

1

0

0

0

 

Example Code

To see the demo result, click on ISE icon inside Seven Segment folder of the CD.

Hardware Settings

Place Jumper at J5 (7SEG) to enable supply to seven segment display.

hardware-settings

Digital Inputs Toggle Switch

The Spartan3 FPGA Kit has eight slide switches, indicated as in Figure 5. The switches connect to an associated FPGA pin, as shown in Table 4. A detailed schematic appears in Figure 5.

slide-switches--tyro-plus

Figure 5. Slide switches connections from Spartan3FPGA Lab Kit

Table 4. FPGA Connections to Slide Switches

Switch

1

2

3

4

5

6

7

8

FPGA pin

P99

P100

P102

P103

P104

P105

P107

P108

  

When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. A 10KΩ series resistor provides nominal input protection.

Example Code

To see the demo result, click ISE icon inside Digital Input Switch folder of the CD

Light Emitting Diodes

Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying pin’s digital states. The Spartan3 FPGA Lab Kit has eight LEDs located above the push button switches, indicated by in Figure 6.

point-led-interface-tyro-plus

Figure 6. Point LED interface from Spartan3FPGA Lab Kit

Table 5. FPGA connections to the LEDs

LED

D1

D2

D3

D4

D5

D6

D7

D8

FPGA   pin

P82

P83

P84

P85

P86

P87

P89

P90

 

The cathode of each LED connects to ground via a 220 ohm Ω resistor. To light an individual LED, drive the associated FPGA control signal High, which is the opposite polarity from lighting one of the 7-segment LEDs.

Example Code

To see the demo result, click on ISE icon inside LED folder of the CD.

Hardware Settings

Place Jumper at J6 (LED) to enable supply to LED.

hardware-settings-tyro-plus

2×16 Graphical LCD

The Spartan3 FPGA Lab kit prominently features a 2×16 liquid crystal display (LCD).The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA to meet the 5V TTL voltage level requirements. The character LCD drives the data lines when LCD_RW is high. Most applications treat the LCD as a write-only peripheral and never read from the display.

Table 6. LCD Connection to FPGA

Signal

FPGA PIN

R/W

P79

RS

P78

E

P80

D0

P82

D1

P83

D2

P84

D3

P85

D4

P86

D5

P87

D6

P89

D7

P90

 

lcd-connections-tyro-plus

Figure 7. LCD connections from Spartan 3 FPGA Kit

Example Code

To see the demo result, click on ISE icon inside LCD folder of the CD.

Hardware Settings

Place Jumper at J7 (LCD) to enable supply to LCD.

hardware-settings-tyro-edk

4 Push Buttons

The Spartan3 FPGA Kit has four contact push button switches, indicated as in Figure 8.

push-button-interface-tyro-plus

Figure 8. Push Button interface from Spartan3 FPGA Kit

Table 7. FPGA Connections to Push Button

Additional information

Weight 1.000000 kg

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