Three Phase Induction Motor Control using TMS320F2812



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Recently the Three Phase inverter and converter have drawn tremendous interest for high voltage and high power application .The general structure of Three Phase inverter and converter is to synthesize sinusoidal voltage waveform from several levels of voltages typically obtained from capacitor voltage source.

Low ratio of carrier frequency to modulation frequency is the best form of modulation for high power application, which is operating domain for multilevel inverter. For this purpose digital control of multilevel inverter using DSP/Microntroller is preferred due to their dynamic controlling property .However DSP/Microntroller based system uses symmetrical regular sampling, asymmetrical regular sampling or re-sampling technique .These sampling techniques either introduces delay in switching or requires dedicated controller .In this work a novel mathematical model of SPWM technique for multilevel inverter is presented which approaches the performance of traditional natural Sinusoidal Pulse width Modulation (SPWM).



2. DSC – TMS320F2812

The Digital Signal Controller (DSC) TMS320F2812 of TEXAS Instrument is used for the implementation of the inverter. TMS320F2812 is a Digital Signal Controller from the C2000 Platform and members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The TYRO TMS320F2812 EVALUATION BOARD is specially designed for developers in dsp field as well as beginners. The F2812 kit is designed in such way that all the possible features of the DSP will be easily used by the everyone.

The kit supports in Code Composer Studio3.3 and later, with XDS100 v1 USB Emulator which is done USB port.



3.1. C28x CPU

The C28x™ DSP generation is the newest member of the TMS320C2000™ DSP platform.

The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by microcontroller devices. This efficiency removes the need for a second processor in many systems.

The 32 x 32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle higher numerical resolution problems that would otherwise demand a more expensive floating-point processor solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a device that is capable of servicing many asynchronous events with minimal latency.

The C28x has an 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware minimizes the latency for conditional discontinuities. Special store conditional operations further improve performance.

3.2. Memory Bus (Harvard Bus Architecture)

The program read bus consists of 22 address lines and 32 data lines. The data read and write busses consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit operations. The multiple bus architecture, commonly termed “Harvard Bus”, enables the C28x to fetch an instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached to the memory bus will prioritize memory accesses. Generally, the priority of Memory

Bus accesses can be summarized as follows:


Data Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Program Writes (Simultaneous data and program writes cannot occur on the memory bus.)

Data Reads & Program Reads (Simultaneous program reads and fetches cannot occur on the memory bus.)


Fetches (Simultaneous program reads and fetches cannot occur on the memory bus.)

3.3. General-Purpose Input/Output (GPIO) Multiplexer

Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO) signals. This multiplexing enables use of a pin as GPIO if the peripheral signal or function is not used. On reset, all GPIO pins are configured as inputs. The user can then individually program each pin for GPIO mode or peripheral signal mode. For specific inputs, the user can also select the number of input qualification cycles to filter unwanted noise glitches.

3.4. 32-Bit CPU-Timers (0, 1, 2)

CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting. When the counter reaches zero, it is automatically reloaded with a 32-bit period value. CPU-Timer 2 is reserved for the DSP/BIOS Real-Time OS, and is connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use. CPU-Timer 1 is for general use and can be connected to INT13 of the CPU. CPU-Timer 0 is also for general use and is connected to the PIE block.

3.5. Control Peripherals

The F281x and C281x support the following peripherals that are used for embedded control and communication:

EV: The event manager module includes

☞general-purpose timers,

☞full-compare/PWM units,

☞capture inputs (CAP) and

☞quadrature-encoder pulse (QEP) circuits.

Two such event managers are provided which enable two three-phase motors to be driven or four two-phase motors. The event managers on the F281x and C281x are compatible to the event managers on the 240x devices (with some minor enhancements).

ADC: The ADC block is a 12-bit converter, single ended, 16-channels. It contains two sample-and-hold units for simultaneous sampling.


4.1. Event Manager Architecture


4.2. PWM Characteristics

Characteristics of the PWMs are as follows:

☞16-bit registers

☞Wide range of programmable deadband for the PWM output pairs

☞Change of the PWM carrier frequency for PWM frequency wobbling as needed

☞Change of the PWM pulse widths within and after each PWM period as needed

☞External-maskable power and drive-protection interrupts

☞Pulse-pattern-generator circuit, for programmable generation of asymmetric, symmetric, and four-space vector PWM waveforms

☞Minimized CPU overhead using auto-reload of the compare and period registers

☞The PWM pins are driven to a high-impedance state when the PDPINTx pin is driven low and after PDPINTx signal qualification. The PDPINTx pin (after qualification) is reflected in bit 8 of the COMCONx register. – PDPINTA pin status is reflected in bit 8 of COMCONA register. – PDPINTB pin status is reflected in bit 8 of COMCONB register.

☞EXTCON register bits provide options to individually trip control for each PWM pair of signals

4.3. Capture Unit

The capture unit provides a logging function for different events or transitions. The values of the selected GP timer counter is captured and stored in the two-level-deep FIFO stacks when selected transitions are detected on capture input pins, CAPx (x = 1, 2, or 3 for EVA; and x = 4, 5, or 6 for EVB). The capture unit consists of three capture circuits.

Capture units include the following features:

☞One 16-bit capture control register, CAPCONx (R/W)

☞One 16-bit capture FIFO status register, CAPFIFOx

☞Selection of GP timer 1/2 (for EVA) or 3/4 (for EVB) as the time base

☞Three 16-bit 2-level-deep FIFO stacks, one for each capture unit

☞Three capture input pins (CAP1/2/3 for EVA, CAP4/5/6 for EVB)—one input pin per capture unit.

[All inputs are synchronized with the device (CPU) clock. In order for a transition to be captured, the input must hold at its current level to meet the input qualification circuitry requirements. The input pins CAP1/2 and CAP4/5 can also be used as QEP inputs to the QEP circuit.]

☞User-specified transition (rising edge, falling edge, or both edges) detection

☞Three maskable interrupt flags, one for each capture unit

☞The capture pins can also be used as general-purpose interrupt pins, if they are not used for the capture function.

4.4. General-Purpose (GP) Timers

There are two GP timers in each EV module. The GP timer

x (x = 1 or 2 for EVA; x = 3 or 4 for EVB) includes:

☞A 16-bit timer, up-/down-counter, TxCNT, for reads or writes

☞A 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), for reads or writes

☞A 16-bit timer-period register, TxPR (double-buffered with shadow register), for reads or writes

☞A 16-bit timer-control register,TxCON, for reads or writes Selectable internal or external input clocks

☞A programmable prescaler for internal or external clock inputs Control and interrupt logic, for four maskable interrupts: underflow, overflow, timer compare, and period interrupts

☞A selectable direction input pin (TDIRx) (to count up or down when directional up-/down-count mode is selected)

The GP timers can be operated independently or synchronized with each other. The compare register associated with each GP timer can be used for compare function and PWM-waveform generation. There are three continuous modes of operations for each GP timer in up- or up/down-counting operations. Internal or external input clocks with programmable prescaler are used for each GP timer. GP timers also provide the time base for the other eventmanager submodules: GP timer 1 for all the compares and PWM circuits, GP timer 2/1 for the capture units and the quadrature-pulse counting operations. Double-buffering of the period and compare registers allows programmable change of the timer (PWM) period and the compare/PWM pulse width as needed.

Mainly The following registers are must to produce simple pwm.

☞TxCNT – Timer x Counter Register

☞TxCMPR – Timer x Compare Register

☞TxPR – Timer x Period Register

☞TxCON – Timer x Control Register

Example: C code to generate the simple 10Khz Pwm.

void main(void)
GpioMuxRegs.GPAMUX.bit.T1PWM_GPIOA6 = 1;
IER = 0x0000;
IFR = 0x0000;
EvaRegs.GPTCONA.bit.TCMPOE = 1; // Drive T1/T2 PWM by compare logic
EvaRegs.GPTCONA.bit.T1PIN = 1; // Polarity of GP Timer 1 Compare = Active low
EvaRegs.T1PR = 0x186A; // Timer1 period for 10 Khz
EvaRegs.T1CMPR = 0x0C35; // Timer1 compare 50 % duty cycle
EvaRegs.T1CNT = 0x0000; // Timer1 counter
EvaRegs.T1CON.all = 0x1042; // TMODE = continuous up mode & enable timer

Period Register Formula is : 


4.5. Full-Compare Units

There are three full-compare units on each event manager. These compare units use GP timer1 as the time base and generate six outputs for compare and PWM-waveform generation using programmable deadband circuit. The state of each of the six outputs is configured independently.

The compare registers of the compare units are double-buffered, allowing programmable change of the compare/PWM pulse widths as needed. These are compare registers: T1CMPR,T2CMPR,CMPR1,CMPR2,CMPR3,T3CMPR,T4CMPR,CMPR4,CMPR5,CMPR6.

4.6. Programmable Deadband Generator

The deadband generator circuit includes three 4-bit counters and an 16-bit compare register. Desired deadband values can be programmed into the compare register for the outputs of the three compare units. The deadband generation can be enabled/disabled for each compare unit output individually. The deadband-generator circuit produces two outputs (with or without deadband zone) for each compare unit output signal.

The output states of the deadband generator are configurable and changeable as needed by way of thedouble-buffered ACTRx register

These are Deaband registers: DBTCONA, DBTCONB

4.7.EV Registers

The EV registers occupy two 64-word (16-bit) frames of address space. The EV module decodes the lower six-bits of the address; while the upper 10 bits of the address are decoded by the peripheral address decode logic, which provides a module select to the Event Manager when the peripheral address bus carries an address within the range designated for the EV on that device.

On 281x devices (as with the C240 device),

☞EVA registers are located in the range 7400h to 7431h.

☞EVB registers are located in the range of 7500h to 7531h.

The undefined registers and undefined bits of the EV registers all return zero when read by user software. Writes have no effect.

5. PWM Waveform Generation

Up to eight PWM waveforms (outputs) can be generated simultaneously by each event manager: three independent pairs (six outputs) by the three fullcompare units with programmable deadbands, and two independent PWMs by the GP-timer compares.

5.1. PWM

A PWM signal is a sequence of pulses with changing pulse widths. The pulses are spread over a number of fixed-length periods so that there is one pulse in each period. The fixed period is called the PWM (carrier) period and its inverse is called the PWM (carrier) frequency

In a motor control system, PWM signals are used to control the on and off time of switching power devices that deliver the desired current and energy to the motor windings

5.1. How to Generate PWM

To generate a PWM signal, an appropriate timer is needed to repeat a counting period that is the same as the PWM period. A compare register is used to hold the modulating values.

The value of the compare register is constantly compared with the value of the timer counter. When the values match, a transition (from low to high, or high to low) happens on the associated output. When a second match is made between the values, or when the end of a timer period is reached, another transition (from high to low, or low to high) happens on the associated output. In this way, an output pulse is generated whose on (or off) duration is proportional to the value in the compare register. This process is repeated for each timer period with different (modulating) values in the compare register. As a result, a PWM signal is generated at the associated output.

5.2. Generation of PWM Output with Event Manager

Each of the three compare units, together with GP timer 1 (in the case of EVA) or GP timer 3 (in the case of EVB), the dead-band unit, and the output logic in the event manager module, can be used to generate a pair of PWM outputs with programmable dead-band and output polarity on two dedicated device pins. There are six such dedicated PWM output pins associated with the three compare units in each EV module. These six dedicated output pins can be used to conveniently control 3-phase ac induction or brushless dc motors.

The flexibility of output behavior control by the compare action control register(ACTRx) also makes it easy to control switched reluctance and synchronous reluctance motors in a wide range of applications. The PWM circuits can also be used to conveniently control other types of motors such as dc brush and stepper motors in single or multi-axis control applications. Each GP timer compare unit, if desired, can also generate a PWM output based on its own timer.

5.2.1 Asymmetric and Symmetric PWM Generation

Both asymmetric and symmetric PWM waveforms can be generated by every compare unit on the EV module. In addition, the three compare units together can be used to generate 3-phase symmetric space vector PWM outputs. PWM generation with GP timer compare units has been described in the GP timer sections. Generation of PWM outputs with the compare units is discussed in this section.

5.2.2 Register Setup for PWM Generation

All three kinds of PWM waveform generations with compare units and associated circuits require configuration of the same Event Manager registers.

The setup process for PWM generation includes the following steps:

☞Setup and load ACTRx

☞Setup and load DBTCONx, if dead-band is to be used

☞Initialize CMPRx

☞Setup and load COMCONx

☞Setup and load T1CON (for EVA) or T3CON (for EVB) to start the operation

☞Rewrite CMPRx with newly determined values

5.2.3 Asymmetric PWM Waveform Generation

The edge-triggered or asymmetric PWM signal is characterized by modulated pulses which are not centered with respect to the PWM period, as shown in figure. To generate an asymmetric PWM signal, GP timer 1 is put in the continuous up-counting mode and its period register is loaded with a value corresponding to the desired PWM carrier period. The COMCONx is configured to enable the compare operation, set the selected output pins to be PWM outputs, and enable the outputs.


If dead-band is enabled, the value corresponding to the required dead-band time should be written by software into the DBT(3:0) bits in DBTCONx(11:8). This is the period for the 4-bit dead-band timers. One deadband value is used for all PWM output channels.

By proper configuration of ACTRx with software, a normal PWM signal can be generated on one output associated with a compare unit while the other is held low (or off) or high (or on), at the beginning, middle, or end of a PWM period. Such software controlled flexibility of PWM outputs is particularly useful in switched reluctance motor control applications.

After GP timer 1 (or GP timer 3) is started, the compare registers are rewritten every PWM period with newly determined compare values to adjust the width (the duty cycle) of PWM outputs that control the switch-on and -off duration of the power devices. Since the compare registers are shadowed, a new value can be written to them at any time during a period. For the same reason, new values can be written to the action and period registers at any time during a period to change the PWM period or to force changes in the PWM output definition.

5.2.4 Symmetric PWM Waveform Generation

A centered or symmetric PWM signal is characterized by modulated pulses which are centered with respect to each PWM period. The advantage of a symmetric PWM signal over an asymmetric PWM signal is that it has two inactive zones of the same duration: at the beginning and at the end of each PWM period. This symmetry has been shown to cause less harmonics than an asymmetric PWM signal in the phase currents of an ac motor, such as induction and dc brushless motors, when sinusoidal modulation is used. Figure shows two examples of symmetric PWM waveforms.


The generation of a symmetric PWM waveform with a compare unit is similar to the generation of an asymmetric PWM waveform. The only exception is that GP timer 1 (or GP timer 3) now needs to be put in continuous up-/down-counting mode.

There are usually two compare matches in a PWM period in symmetric PWM waveform generation, one during the upward counting before period match, and another during downward counting after period match. A new compare value becomes effective after the period match (reload on period) because it makes it possible to advance or delay the second edge of a PWM pulse. An application of this feature is when a PWM waveform modification compensates for current errors caused by the dead-band in ac motor control.

Because the compare registers are shadowed, a new value can be written to them at any time during a period. For the same reason, new values can be written to the action and period registers at any time during a period to change the PWM period or to force changes in the PWM output definition.

5.3. Why Deab Band

In many motion/motor and power electronics applications, two power devices, an upper and a lower, are placed in series on one power converter leg. The turn-on periods of the two devices must not overlap with each other in order to avoid a shoot-through fault. Thus, a pair of non-overlapping PWM outputs is often required to properly turn on and off the two devices.

A dead time (deadband) is often inserted between the turning-off of one transistor and the turning- on of the other transistor. This delay allows complete turning-off of one transistor before the turning – on of the other transistor. The required time delay is specified by the turning-on and turning-off characteristics of the power transistors and the load characteristics in a specific application.

6. Sinusoidal PWM

Sinusoidal pulse width modulation is a method of pulse width modulation used in inverters. An inverter produces an AC output voltage from a DC input by using switching circuits to simulate a sine wave by producing one or more square pulses of voltage per half cycle. If the widths of the pulses are adjusted as a means of regulating the output voltage, the output is said to be pulse width modulated.

With sinusoidal or sine weighted pulse width modulation, several pulses are produced per half cycle. The pulses near the edges of the half cycle are always narrower than the pulses near the center of the half cycle such that the pulse widths are proportional to the corresponding amplitude of a sine wave at that portion of the cycle. To change the effective output voltage, the widths of all pulses are increased or decreased while maintaining the sinusoidal proportionality. With pulse width modulation, only the widths (on-time) of the pulses are modulated. The amplitudes (voltage) during the “on-time” is constant unless a multi-step circuit is used. The line-to neutral voltage of a 3-phase inverter has two voltage levels.


The easiest way to generate a sinusoidal waveform is to use a lookup table. You could also calculate the sine value on the fly, but it’s just not worth spending the CPU time to do this. A lookup table is used that contains all the points of a sine value. The sine values are read from the table at periodic intervals, scaled to match the allowable range of duty cycles, and then written to the duty cycle registers.

The sine table values are stored in program memory. It is transferred data to data memory during initialization for faster access. Three registers are used as offsets to the table through indirect addressing. An array is defined the current location of the lookup table. A counter variable is added to this array at each interval, the software will move through the table at affixed frequency. The lookup table usually contains from 0 to 256 data.

The offset values are added to the sine table array values at each PWM interrupt . The 180 degrees phase shift is loaded into phases. Once lookup table values are obtained from the table, they are multiplied by scaling values to determine the actual amplitude of the modulation output.

Two inverted pulses are generated with dead band by using PWM Generator for a Three Phase PWM Inverter. The PWM interrupt is enabled when internal counter reaches the period register value. When PWM interrupt occurring, a single data is taking from lookup table. The lookup table contains 256 sampling data by using the sine formula,


Where, i – 0 to 256. Π – 3.14.

The main program determines the voltage, amplitude and frequency while PWM ISR realizes the PWM by setting the proper compare registers values, dead band timer control register and timer period register, etc.

The PWM ISR flow chart as shown in below,


Spwm will trigger the IGBT in the following manner.,

Inverter in Power-Electronics refers to a class of power conversion circuits that operate from a dc voltage source or a dc current source and convert it into a symmetric ac voltage or current. It does reverse of what ac-to-dc ‘converter’ does.

A DC to AC voltage converter consists of four bidirectional switches that is used to convert the voltage. Sinusoidal unipolar Pulse Width Modulation is used for triggering the gates of IGBTs. The control circuit consists of the DSC controller and it is used to produce required SPWM for triggering the IGBTs. The driver circuit isolates the control circuit from power circuit. The outputs for variable AC voltages are observed in the CRO.

A PWM period register is used to generate the PWM frequency range. The PWM period register calculation is:


Sinusoidal triangle PWM (SPWM) is the mostly used method. Triangle wave is used as carrier and reference signal is sinusoidal wave, whose frequency is the desired frequency and amplitude is determined by desired voltage amplitude, DC voltage and carrier amplitude. Two separate single-phase inverters where each inverter produces an output delayed by 180° (of the fundamental frequency) with respect to each other. The Three Phase Sinusoidal PWM inverter output pulses are shown in below,


Fig. 4 Three Phase Sinusoidal PWM inverter waveform outputs


Fig. 5 Sinusoidal PWM Output Pulses

To drive a PWM inverter, a three phase inverter bridge is driven by a microcontroller outputs. By changing the PWM duty cycles in a regular manner, the PWM outputs are modulated to synthesize the sinusoidal waveform. The Three Phase PWM inverter Mode is accomplished with the PWM peripheral operated in complementary mode with dead time.

7. Three Phase Sine PWM Inverter PULSES

In Three Phase Sine PWM Inverter, Totally six Pwm is required pwm1,pwm2,pwm3,pwm4,pwm5,pwm6 required to run a three phase induction motor. The Three phase sine PWM pulse pattern are listed below

☞Pwm1 – active high.

☞Pwm2 – active low and inverted of pwm1.

☞Pwm3 – active high and 120° phase shift of pwm1.

☞Pwm4 – active low and inverted of pwm3.

☞Pwm5 – active high and 240° phase shift of pwm1.

☞Pwm6 – active low and inverted of pwm5.

And keep 4µs deadband between pwm1 & pwm2 , pwm3 & pwm4 and also between pwm5 and pwm6. These pwm are feeding to driver circuit for controlling the Three phase induction motor. The Motor is coming together with proximity sensor to read speed.

One capture is used to read a speed. Example proximity sensor. This sensor is installed at motor side, it feed the some signal to DSC. The proximity sensor will produce a 50 Hz square wave for maximum motor speed. Accordingly ,we have to claculate the speed by using any of the capture pin.

Two input keys are used to set the RPM and also we executing the PID loop at every 10 milli seconds. The PID loop update the step frequency and amplitude percentage at particular variable. While compare interrupt ISR executing the frequency and amplitude values will updates to that particular registers. Restrict the amplitude as after 90% keep as constant 90%.

First two keys are used to vary ( increase or decrease ) a RPM. The next two keys are used to vary ( increase or decrease ) a Kp contant then the next two keys are used to vary ( increase or decrease ) a Ki contant.

Program flow chart:










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