SPST BASED POWER OPTIMIZED MULTIPLIER

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SPST BASED POWER OPTIMIZED MULTIPLIER
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SPST BASED POWER OPTIMIZED MULTIPLIER
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INTRODUCTION
Multiplication can be considered as a series of repeated additions.The number to be added is the multiplicand; the number of times that it isadded is the multiplier; and the result is the product. Each step of additiongenerates a partial product. In most computers, the operand usually contains he same number of bits. When the operands are interpreted as integers, the product is generally twice the length of operands in order to preserve the information content. This repeated addition method that is suggested by the arithmetic definition is slow that it is almost always replaced by an algorithm that makes use of positional representation. It is possible to decompose
multipliers into two parts. The first part is dedicated to the generation of partial products, and the second one collects and adds them. As for adders, it is possible to enhance the intrinsic performance of multipliers. Acting in the generation part, the booth algorithm is often used because it reduces the number of partial products. Multiplication occurs frequently in finite impulse response filters, Fast Fourier transforms, discrete cosine transforms, convolution, and other important DSP and multimedia
kernels. Owing to the importance of multiplication in DSP and multimedia applications, several designs have been developed for sub word-parallel
multipliers and Multiply-And-Accumulate (MAC) units. The objective of a25 good multiplier is to provide a physically compact, good speed and low power onsuming chip.
The basic multiplication principle is two fold:
x evaluation of partial products and
x accumulation of the shifted partial products
Tools required:
Xilinx 14.7
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