# LScheme VLSI LAB Experiments for Spartan-3 FPGA Starter kit

## PSTYRO-FPGASP3 lscheme Manual

Tags: Anna university vlsi lab experiments for L scheme,k scheme vlsi lab experiments,l scheme vlsi lab experiment, jntu vlsi lab experiments,,
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##### Description

Optimize a 4 variable combinational function (SOP or POS), describe it in VHDL code and Simulate it.

Example: F= (0, 5, 8, 9, 12) in sop

##### Truth Table for Sum of Product Simplification

 A B C D Y Sum of Product 0 0 0 0 1 A’B’C’D’ 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 1 1 A’BC’D 0 1 1 0 0 0 1 1 1 0 1 0 0 0 1 AB’C’D’ 1 0 0 1 1 AB’C’D 1 0 1 0 0 1 0 1 1 0 1 1 0 0 1 ABC’D’ 1 1 0 1 0 1 1 1 0 0 1 1 1 1 0

##### Boolean Expression:

Y = A’B’C’D’+A’BC’D+AB’C’D’+AB’C’D+ABC’D’

Y = B’C’D’(A’+A) +C’(A’BD+AB’D+ABD’)

Y = B’C’D’+A’BC’D+AB’C’D+ABC’D’

##### Code Listing

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity sop is

port(a,b,c,d : in std_logic;

y : out std_logic

);

end sop;

architecture data of sop is

begin

y <= (( not b and not c and not d) or (not a and b and not c and d) or (a and not b and not c and  d) or (a and  b and not c and not d) );

end data;

##### Input Waveform

We give input a=high in waveform window

##### Output waveform

We give input a=high in waveform window

##### Description

Optimize a 4 variable combinational function (POS), describe it in VHDL code and Simulate it.

Example: F= (0, 5, 8, 9, 12) in POS.

##### Truth Table for Product of Sum Simplification

 A B C D Y Product of Sum 0 0 0 0 1 0 0 0 1 0 A’+B’+C’+D 0 0 1 0 0 A’+B’+C+D’ 0 0 1 1 0 A’+B’+C+D 0 1 0 0 0 A’+B+C’+D’ 0 1 0 1 1 0 1 1 0 0 A’+B+C+D’ 0 1 1 1 0 A’+B+C+D 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0 A+B’+C+D’ 1 0 1 1 0 A+B’+C+D 1 1 0 0 1 1 1 0 1 0 A+B+C’+D 1 1 1 0 0 A+B+C+D’ 1 1 1 1 0 A+B+C+D

Y = (A’+B’+C’+D ) (A’+B’+C+D’) (A’+B’+C+D) (A’+B+C’+D’) (A’+B+C+D’) (A’+B+C+D) (A+B’+C+D’) (A+B’+C+D) (A+B+C’+D) (A+B+C+D’) (A+B+C+D)

##### Code Listing

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity pos is

port(a,b,c,d : in std_logic;

y : out std_logic

);

end pos;

architecture data of pos is

begin

y <= ((not a or not b or not c or  d ) and(not a or not b or  c or not  d) and (not a or not b or  c or  d) and (not a or   b or not c or not d)and (not a or b or  c or not d)and(not a or b or c or d) and (a or not b or c not d) and (a or not b or c or d)and(a or b or not c or d  ) and (a or b or c or not d) and (a or b  or c or d)) ;

end data;

##### Input Waveform

We give input a=high in waveform window

##### Output waveform

Finally we get output in simulation window(y=high according to that POS Equation)

##### Description

Design and Develop the circuit for the following arithmetic function in VHDL Codes and Simulate it. Addition, Subtraction Multiplication (4 x 4 bits)

It is possible to create a logical circuit using multiple full adders to add N-bit numbers. Each full adder inputs a Cin, which is the Cout of the previous adder. This kind of adder is called a ripple-carry adder, since each carry bit "ripples" to the next full adder.

The full-adder circuit adds three one-bit binary numbers (Cin, A, B) and outputs two one-bit binary numbers, a sum (S) and a carry (Cout).

##### Code:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

Port ( x: in  STD_LOGIC_VECTOR (3 downto 0);

y : in  STD_LOGIC_VECTOR (3 downto 0);

cin : in  STD_LOGIC;

sum : out  STD_LOGIC_VECTOR (3 downto 0);

cout : out  STD_LOGIC);

port(

x,y,cin:in std_logic;

sum,cout: out std_logic);

end component;

signal c: std_logic_vector(2 downto 0);

begin

a1:fulladder port map(x(0), y(0), cin, sum(0), c(0));

a2:fulladder port map(x(1), y(1), c(0), sum(1), c(1));

a3:fulladder port map(x(2), y(2), c(1), sum(2), c(2));

a4:fulladder port map(x(3), y(3), c(2), sum(3), cout);

end Behavioral;

library ieee;

use ieee.std_logic_1164.all;

port(

x,y,cin:in std_logic;

sum,cout: out std_logic);

begin

sum <= x xor y xor cin;

cout <= (x and y) or (cin and (x xor y));

end comb;

##### Input Wave form

We give input x=’1’, y=’1’ and cin=’1’in waveform window

##### Output Wave form

We give input x=’1’, y=’1’ and cin=’1’ so we get sum=’3’waveform window

###### 2.2 Subtraction (Program for 4-bit subtraction using arithmetic operator)

It is possible to create a logical circuit using multiple full subtractor to subtract N-bit numbers. Each full subtractor inputs a Bin, which is the Bout of the previous subtractor . This kind of subtractor is called a ripple-carry subtractor, since each Borrow bit "ripples" to the next full subtractor.

##### Full Subtractor

A combinational circuit which performs the subtraction of three input bits is called full subtractor. The three input bits include two significant bits and a previous borrow bit.

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sub is

Port ( a: in  STD_LOGIC_VECTOR (3 downto 0);

b : in  STD_LOGIC_VECTOR (3 downto 0);

bin : in  STD_LOGIC;

Diff : out  STD_LOGIC_VECTOR (3 downto 0);

bout : out  STD_LOGIC);

end  sub;

architecture Behavioral of sub is

component fullsub

port(

a,b,bin:in std_logic;

Diff,bout: out std_logic);

end component;

signal D: std_logic_vector(2 downto 0);

begin

x1:fullsub port map(a(0), b(0), bin, Diff(0), D(0));

x2:fullsub port map(a(1), b(1), D(0), Diff(1), D(1));

x3:fullsub port map(a(2), b(2), D(1), Diff(2), D(2));

x4:fullsub port map(a(3), b(3), D(2), Diff(3), Bout);

end Behavioral;

library ieee;

use ieee.std_logic_1164.all;

entity fullsub is

port(

a,b,bin:in std_logic;

Diff,bout: out std_logic);

end fullsub;

architecture comb of fullsub is

begin

Diff <= a xor b xor bin;

bout <= ((not a )and b) or ((not bin )and (a xor b)) ;

end comb;

##### Input Waveform

We give input a=’1010’, b=’0101’ in waveform window

##### Output Waveform

We get output in simulation window( according to that subtraction Operation)

###### 2.3 Multiplication (Program for simple 4x4 multiplications using arithmetic operator)

Consider the multiplication of two numbers as 4 x4 a * b, where a and b are 4 bit numbers and the output of multiplication is taken in y as 8 bit number.

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity codef is

Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);

b : in  STD_LOGIC_VECTOR (3 downto 0);

y : out  STD_LOGIC_VECTOR (7 downto 0));

end codef;

architecture Behavioral of codef is

begin

y <= a * b;

end Behavioral;

##### Input Waveform

We give input a =’2’& b =’2’ .

##### Output Waveform

We give input a =’2’& b =’2’ .so, we get output y=’4’ according to that multiplication operation.

##### Description

Design and develop a 2 bit multiplexer and port map the same for developing up to 8 bit multiplexer.

##### Multiplexer

A multiplexer is a combinatorial circuit that is given a certain number (usually a power of two) data inputs, let us say 2n, and n address inputs used as a binary number to select one of the data inputs. The multiplexer has a single output, which has the same value as the selected data input.

In other words, the multiplexer works like the input selector of a home music system. Only one input is selected at a time, and the selected input is transmitted to the single output. While on the music system, the selection of the input is made manually, the multiplexer chooses its input based on a binary number, the address input.

The truth table for a multiplexer is huge for all but the smallest values of n. We therefore use an abbreviated version of the truth table in which some inputs are replaced by `-' to indicate that the input value does not matter.

Here is such an abbreviated truth table for n = 3. The full truth table would have 2(3 + 23) = 2048 rows.

##### 2:1 multiplexer program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity mux is

Port ( x : in  STD_LOGIC;

y : in  STD_LOGIC;

sel : in  STD_LOGIC;

z : out  STD_LOGIC);

end mux;

architecture Behavioral of mux is

begin

process (x,y,sel)

begin

if(sel='0') then

z<=x;

elsif (sel='1') then

z<=y;

end if;

end process;

##### 8:1 mux port map program

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity multiplexer is

Port (

a, b,c,d,e,f,g,h : in  STD_LOGIC ;

c0,c1,c2: in std_logic;

z : out  STD_LOGIC );

end multiplexer;

architecture Behavioral of multiplexer is

component mux

port(

x:in std_logic;

y: in std_logic;

sel: in std_logic;

z: out std_logic

);

end component ;

signal z1,z2,z3,z4,z5,z6 : std_logic :='0';

begin

signal z1,z2,z3,z4,z5,z6 : std_logic :='0';

begin

mux1: mux port map (a, b, c0, z1);

mux2: mux port map (c, d, c0, z2);

mux3: mux port map (e, f, c0, z3);

mux4  mux port map (g, h, c0, z4);

mux5: mux port map (z1, z2, c1, z5);

mux6: mux port map (z3, z4, c1, z6);

mux7: mux port map (z5, z6, c2, z);

end Behavioral;

##### Input Waveform

We give input a=’high’ in waveform window

##### Output Waveform

We get output in simulation window (y=’high’ according to that multiplexer operation)

##### Description

Design and develop an 8 output demultiplexer using truth table.

##### Demultiplexer

The demultiplexer is the inverse of the multiplexer, in that it takes a single data input and n address inputs. It has 2n outputs. The address input determine which data output is going to have the same value as the data input. The other data outputs will have the value 0.

Here is an abbreviated truth table for the demultiplexer. We could have given the full table since it has only 16 rows, but we will use the same convention as for the multiplexer where we abbreviated the values of the data inputs.

 `S2` `S1` `S0` `E` `Y7` `Y6` `Y5` `Y4` `Y3` `Y2` `Y1` `Y0` `0` `0` `0` `1` `0` `0` `0` `0` `0` `0` `0` `1` `0` `0` `1` `1` `0` `0` `0` `0` `0` `0` `1` `0` `0` `1` `0` `1` `0` `0` `0` `0` `0` `1` `0` `0` `0` `1` `1` `1` `0` `0` `0` `0` `1` `0` `0` `0` `1` `0` `0` `1` `0` `0` `0` `1` `0` `0` `0` `0` `1` `0` `1` `1` `0` `0` `1` `0` `0` `0` `0` `0` `1` `1` `0` `1` `0` `1` `0` `0` `0` `0` `0` `0` `1` `1` `1` `1` `1` `0` `0` `0` `0` `0` `0` `0`

##### Here is one possible circuit diagram for the demultiplexer:

In this program a 1 x 8 de-multiplexer have two 1- bit inputs, a 3-bit select line and a 8- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.

##### Code Listing

library ieee;

use ieee.std_logic_1164.all;

entity demultiplexer is

port(I : in std_logic;

s : in std_logic_vector(0 to 2);

O : out std_logic_vector(0 to 7));

end demultiplexer;

architecture data of demultiplexer is

begin

O(0) <= (I and not s(0) and not s(1) and not s(2));

O(1) <= (I and s(0) and not s(1) and not s(2));

O(2) <= (I and not s(0) and s(1) and not s(2));

O(3) <= (I and s(0) and s(1) and not s(2));

O(4) <= (I and not s(0) and not s(1) and s(2));

O(5) <= (I and s(0) and not s(1) and s(2));

O(6) <= (I and not s(0) and s(1) and s(2));

O(7) <= (I and s(0) and s(1) and s(2));

end data;

##### Input Waveform

We put enable as high in all condition and here we give input=’010’ in selection line(according to that selection line we get output)

##### Output Waveform

We get output in simulation window(according to that selection line)

##### Description

Describe the code for a multiplexer and implement it in FPGA kit in which switches are connected for select input and for data inputs a LED is connected to the output.

##### PIN Description:

 I/O Pins A B C D SEL0 SEL1 OUTPUT FPGA LOC P86 P87 P89 P90 P92 P93 P105

##### Code Listing

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity mux_gate is

port (A,B,C,D: in STD_LOGIC;

SEL     : in STD_LOGIC_vector (1 downto 0);

Output    : out STD_LOGIC);

end mux_gate;

architecture behav of mux_gate is

begin

process (SEL,A,B,C,D)

begin

case SEL is

when "00"  => Output <= A;

when "01"  => Output <= B;

when "10"  => Output <= C;

when "11"  => Output <= D;

when others => null;

end case;

end process;

end behave;

##### Description

Switches are connected for select inputs and a data input, Eight LEDs are connected to the output of the circuit.

##### PIN Description:

 I/O PINS E S(0) S(1) S(2) Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) FPGA LOC P86 P87 P89 P90 P97 P98 P99 P100 P102 P103 P104 P105

##### Code Listing

library ieee;

use ieee.std_logic_1164.all;

entity demultiplexer is

port(e : in std_logic;

s : in std_logic_vector(0 to 2);

y : out std_logic_vector(0 to 7));

end demultiplexer;

architecture data of demultiplexer is

begin

y(0) <= (e and not s(0) and not s(1) and not s(2));

y(1) <= (e and s(0) and not s(1) and not s(2));

y(2) <= (e and not s(0) and s(1) and not s(2));

y(3) <= (e and s(0) and s(1) and not s(2));

y(4) <= (e and not s(0) and not s(1) and s(2));

y(5) <= (e and s(0) and not s(1) and s(2));

y(6) <= (e and not s(0) and s(1) and s(2));

y(7) <= (e and s(0) and s(1) and s(2));

end data;

##### Description

Develop Boolean expression for 4 input variables and 7 output variables. Design and develop seven segment decoder in VHDL for 7 equations. A seven segment display is connected to the output of the circuit. Four switches are connected to the input. The 4 bit input is decoded to 7 segment equivalent.

##### PIN Description:

 I/O PINS I0 I1 I2 I3 A B C D E F G FPGA LOC P86 P87 P89 P90 P23 P24 P25 P26 P27 P28 P30

 SEL0 SEL1 SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 P12 P13 P14 P15 P17 P18 P20 P21

##### Look Up Table:

 I3 I2 I1 I0 G F E D C B A 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity seven_seg is

Port ( I3,I2,I1,I0 : in  STD_LOGIC;

sel : out std_logic_vector (3 downto 0);

A,B,C,D,E,F,G : out  STD_LOGIC);

end seven_seg;

architecture Behavioral of seven_seg is

SIGNAL X0,X1,X2,X3,X4,X5,X6,X7,X8,X9:STD_LOGIC;

begin

sel <= "11111111";

X0<= (NOT I3 AND NOT I2 AND NOT I1 AND NOT I0);
X1<= (NOT I3 AND NOT I2 AND NOT I1 AND I0);
X2<= (NOT I3 AND NOT I2 AND I1 AND NOT I0);
X3<= (NOT I3 AND NOT I2 AND I1 AND I0);
X4<= (NOT I3 AND I2 AND NOT I1 AND NOT I0);
X5<= (NOT I3 AND I2 AND NOT I1 AND I0);
X6<= (NOT I3 AND I2 AND I1 AND NOT I0);
X7<= (NOT I3 AND I2 AND I1 AND I0);
X8<= (I3 AND NOT I2 AND NOT I1 AND NOT I0);
X9<= (I3 AND NOT I2 AND NOT I1 AND I0);

A <= X1 OR X4;
B <= X5 OR X6;
C <= X2;
D <= X1 OR X4 OR X7 OR X9;
E <= X1 OR X3 OR X4 OR X5 OR X7 OR X9;
F <= X1 OR X2 OR X3 OR X7;
G <= X0 OR X1 OR X7;

end Behavioral;

##### Description

Develop a 7 segment decoder using Look up table. Describe the seven segment decoder in VHDL using developed Look up table. A seven segment display is connected to the output of the circuit. Four switches are connected to the input. The 4 bit input is decoded into 7 segment equivalent.

##### Look Up Table:

 I3 I2 I1 I0 G F E D C B A 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 0 1 0 0 0 0 0 1 1 0 0 0

##### PIN Description:

 I/O PINS I0 I1 I2 I3 A B C D E F G FPGA LOC P86 P87 P89 P90 P23 P24 P25 P26 P27 P28 P30

 SEL0 SEL1 SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 P12 P13 P14 P15 P17 P18 P20 P21

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity SEVEN_SEG_LUT is

Port ( I : in  STD_LOGIC_VECTOR (3 downto 0);

SEL : out  STD_LOGIC_VECTOR (7 downto 0);

Y : out  STD_LOGIC_VECTOR (6 downto 0));

end SEVEN_SEG_LUT;

architecture Behavioral of SEVEN_SEG_LUT is

begin

SEL <= "11111111";

process (I)

BEGIN

case  I is

when "0000"=> Y <="1000000";  -- '0'

when "0001"=> Y <="1111001";  -- '1'

when "0010"=> Y <="0100100";  -- '2'

when "0011"=> Y <="0110000";  -- '3'

when "0100"=> Y <="0011001";  -- '4'

when "0101"=> Y <="0010010";  -- '5'

when "0110"=> Y <="0000010";  -- '6'

when "0111"=> Y <="1111000";  -- '7'

when "1000"=> Y <="0000000";  -- '8'

when "1001"=> Y <="0011000";  -- '9'

when others=> Y <="1111111";

end case;

end process;

end Behavioral;

##### Encoder:

Design and develop HDL code for decimal (Octal) to BCD encoder. There will be10 input switches (or 8 switches) and 4 LEDs in the FPGA kit. The input given from switches and it is noted that any one of the switch is active. The binary equivalent for the corresponding input switch will be glowing in the LED as output

##### PIN Description:

 I/O PINS X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7) A B C D FPGA LOC P86 P87 P89 P90 P92 P93 P95 P96 P97 P98 P99 P100

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( x : in std_logic_vector(7 downto 0);

a,b,c,d : out std_logic;);

end first;

architecture Behavioral of first is

begin

a <= x(1) or x(3) or x(5) or x(7) or x(9);

b <= x(2) or x(3) or x(6) or x(7) ;

c <= x(4) or x(5) or x(6) or x(7) ;

d <= x(9) or x(8) ;

end Behavioral;

##### Description

Develop a VHDL code for making a delayed output for 1second or 2 seconds by assuming clock frequency provided in the FPGA Kit. Simulate same code to get a delayed waveform.

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( clock : in std_logic;

a     : out std_logic);

end first;

architecture Behavioral of first is

begin

process(clock)

variable i : integer := 0;

begin

if clock'event and clock = '1' then

if i <= 50000000 then

i := i + 1;

a <= '1';

elsif i > 50000000 and i < 100000000 then

i := i + 1;

a <= '0';

elsif i = 100000000 then

i := 0;

end if;

end if;

end process;

end Behavioral;

##### Input Waveform

We give input in waveform window (clk=’1’)

##### Output Waveform

We get output in simulation waveform (a=’delayed signal’)

##### Description

Develop a VHDL Code for delay and verify by simulating it. This delay output is connected to LED. Delay is adjusted such away LED blinks for every 1 or 2 seconds.

##### PIN Description:

 I/O PINS CLK LED FPGA LOC P55 P97

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( clock : in std_logic;

LED     : out std_logic);

end first;

architecture Behavioral of first is

begin

process(clock)

variable i : integer := 0;

begin

if clock'event and clock = '1' then

if i <= 50000000 then

i := i + 1;

LED <= ‘0’;

elsif i > 50000000 and i < 100000000 then

i := i + 1;

LED <= ‘1’;

elsif i = 100000000 then

i := 0;

end if;

end if;

end process;

end Behavioral;

##### Description

Develop a VHDL test bench code for testing any one of the simple gate. Simulate the test bench code in the HDL software.

##### Code Listing (AND gate program)

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gate is

Port ( a : in  STD_LOGIC;

b : in  STD_LOGIC;

c : out  STD_LOGIC);

end gate;

architecture Behavioral of gate is

begin

c <= a and  b;

end Behavioral;

##### Testbench code

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY code_vhd IS

END code_vhd;

ARCHITECTURE behavior OF code_vhd IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT cd

PORT(

a : IN std_logic;

b : IN std_logic;

c : OUT std_logic

);

END COMPONENT;

--Inputs

SIGNAL a :  std_logic := '0';

SIGNAL b :  std_logic := '0';

--Outputs

SIGNAL c :  std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: cd PORT MAP(

a => a,

b => b,

c => c

);

tb : PROCESS

BEGIN

a<='1';

b<='1';

-- Wait 100 ns for global reset to finish

wait for 100 ns;

a<='1';

b<='0';

-- Place stimulus here

wait for 100 ns; -- will wait forever

END PROCESS;

END;

##### Output Waveform

We get output in simulation window (c=’1’ according to that gate operation)

##### Description

Design and develop a VHDL Code for 4 bit binary up counter. Four LEDs are connected at the output of the counter. The counter should up for every one seconds.

##### PIN Description:

 I/O PINS CLOCK RST Q(3) Q(2) Q(1) Q(0) FPGA LOC P55 P86 P97 P98 P99 P100

##### Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( clock : in std_logic;

rst:in std_logic;

q     : out std_logic_vector(3 downto 0);

end first;

architecture Behavioral of first is

signal tmp: std_logic_vector(3 downto 0):="0000";

begin

process(clock ,rst)

variable i : integer := 0;

begin

if (rst='1') then

tmp <= "0000";

elsif clock'event and clock = '1' then

if i <= 50000000 then

i := i + 1;

elsif i = 50000001 then

i := 0;

tmp <= tmp+1;

end if;

end if;

end process;

q<= tmp;

end Behavioral;

##### Description

Design and develop VHDL Code for a 5 bit Johnson ring counter 4 bit The LEDs are connected at the output of the counter. The speller should work for every one seconds.

##### PIN Description:

 I/O PINS CLOCK RST Q(4) Q(3) Q(2) Q(1) Q(0) FPGA LOC P55 P86 P97 P98 P99 P100 P102

##### CODE Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity first is

port ( clk : in std_logic;

Reset: in std_logic;

output : out std_logic_vector(4 downto 0));

end first;

architecture Behavioral of first is

signal temp: std_logic_vector(4 downto 0):=”00000”;

begin

process(clk, Reset)

variable i,k : integer := 0;

begin

if Reset = ‘1’ then

temp <= “00000”;

elsif clk'event and clk = '1' then

if i < 50000000 then

i := i + 1;

elsif i = 50000000 then

temp(1) <= temp(0);

temp(2) <= temp(1);

temp(3) <= temp(2);

temp(4) <= temp(3);

temp(0) <= not temp(4);

i:=0;

end if;

end if;

end process;

Reset <= temp;

End Behavioral;

##### Description

Design and develop a seven segment decoder in VHDL. Design and develop a 4 bit BCD counter, the output of the counter is given to seven segment decoder. A seven segment display is connected to the output of the decoder. The display shows 0,1, 2.. 9 for every one second

##### PIN Description:

 I/O PINS CLK Y(0) Y(1) Y(2) Y(3) Y(4) Y(5) Y(6) Y(7) FPGA LOC P55 P23 P24 P25 P26 P27 P28 P30 P31

 SEL0 SEL1 SEL2 SEL3 SEL4 SEL5 SEL6 SEL7 P12 P13 P14 P15 P17 P18 P20 P21

##### Code Lisitng

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity object_co  is

port(clk    : in  std_logic;

y      : out std_logic_vector(7 downto 0);

sel     : out std_logic_vector(7 downto 0)

);

end object_co;

architecture beav of object_co  is

type state is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9);

signal next_state,ps: state := state0;

begin

sel <= "11111111";

process(clk,next_state)

variable i : integer := 0 ;

begin

if clk'event and clk = '1' then

if i <= 100000000 then

i := i + 1;

elsif i > 100000000 then

i := 0 ;

next_state <= ps ;

end if;

if next_state = state0 then

y <= x"c0" ;

ps <= state1;

elsif next_state = state1 then

y <= x"f9";

ps <= state2;

elsif next_state = state2 then

y <= X"a4";

ps <= state3;

elsif next_state = state3 then

y <= X"b0";

ps <= state4;

elsif next_state = state4 then

y <= X"99";

ps <= state5;

elsif next_state = state5 then

y <= X"92";

ps <= state6;

elsif next_state = state6 then

y <= X"82";

ps <= state7;

elsif next_state = state7 then

y <= X"f8";

ps <= state8;

elsif next_state = state8 then

y <= X"80";

ps <= state9;

elsif next_state = state9 then

y <= X"98";

ps <= state0;

end if;

end if;

end process;

end beav;