Forums CPLD/FPGA Boards Xilinx FPGA How to configure the delay in FPGA

How to configure the delay in FPGA

Link to this post 18 Jan 14


I Had the pantech FPGA (xc3s200)kit.i have doubt in the delay you calculate the delay as please explain the calculation method.

Link to this post 20 Jan 14

Hello Karthikeyan,
welcome to pantech Solutions forum. Your question arise from the How to Article section below.

Interfacing leds with spartan-6 FPGA
Spartan-6 FPGA Development Kit

The Spartan-6 FPGA Board fed with 50MHz crystal oscillator to provide clock input to FPGA.
50MHz clock generate a delay of 20 nano sec. To ON/OFF LED after every 1 sec, the following formula should be applied.

20 ns = FPGA Clock
1 sec = Output Delay

20 ns = 1 sec / 50MHz
20 x 10^-9 = 1 sec / 50 x 10^6

20 x 10^-9 x 50 x 10^6 = 1 sec

FPGA Clock x 50 x 10^6 = Output delay

From the above equation, To generate 1 sec delay we need to multiply the FPGA clock with 50000000 using counter. when counter reach 50000000 delay led value get toggeled.


Link to this post 27 Jan 14

I want spatran 3E FPGA materiel with images.please sent for my project
thank you.........

Link to this post 27 Jan 14

You could download materials from tutorials and source code section from the below link

Link to this post 28 Jan 14

Hi Venkat,
What kind of material you are looking for? If you already purchased Spartan-3e FPGA Board you can download related documents in the Tutorial and How to articles page of FPGA board.