Wavelet techniques can be successfully applied in various signal and image processing applications, namely in image de-noising, segmentation, classification, motion estimation and copy right protection. The proliferation of digitized media due to the rapid growth of networked multimedia systems has created an urgent need for copyright enforcement technologies that can protect copyright ownership of multimedia objects. Digital image watermarking is one such technology that has been developed to protect digital images from illegal manipulations.
In this paper, a robust and imperceptible watermarking scheme for copy right protection is proposed. The method is based on decomposing an image using the discrete wavelet transform, and then embedding locations are generated from the low frequency sub-band by using secrete sort to improve the embedding intensity. From the experimental results, the proposed scheme provides not only good quality, but also good robustness against external attacks, such as rotation, compression, cropping, noise and scaling.
The ADSP-BF533/32/31 processors are enhanced members of the Blackfin processor family that offer significantly higher performance and lower power than previous Blackfin processors while retaining their ease-of-use and code compatibility benefits, processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory.
The Blackfin processor core architecture combines a dual MAC signal processing engine, an orthogonal RISC-like microprocessor instruction set, flexible Single Instruction, Multiple Data (SIMD) capabilities, and multimedia features into a single instruction set architecture. Blackfin products feature dynamic power management. The ability to vary both the voltage and frequency of operation optimizes the power consumption profile to the specific task.
The BLACKFIN EVALUATION BOARD is specially designed for developers in dsp field as well as beginners. The BF532 kit is designed in such way that all the possible features of the DSP will be easily used by everyone. The kit supports in VisualDsp++5.0 and later.
The Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection.
The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.
The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.
Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only.
Digital watermarking is the process of computer-aided information hiding in a carrier signal; but does not need to contain a relation to the carrier signal. Digital watermarks may be used to verify the authenticity or integrity of the carrier signal or to show the identity of its owners.
It is prominently used for tracing copyright infringements and for banknote authentication. Like traditional watermarks, digital watermarks are only perceptible under certain conditions, i.e. after using some algorithm, and imperceptible anytime else. If a digital watermark distorts the carrier signal in a way that it gets perceivable, it is of no use.
Traditional Watermarks may be applied to visible media (like images or video), whereas in digital watermarking, the signal may be audio, pictures, video, texts or 3D models.
A signal may carry several different watermarks at the same time. Unlike metadata that is added to the carrier signal, a digital watermark does not change the size of the carrier signal.
The following are playing a major in our project:
The Blackfin Evaluation Board has 128Mbit SDRAM interfaced in BF532 kit. This interface will use to store a huge data (pixel) .
The RS232 9 pin serial communication is interfaced through UART Serial Interface peripheral. This interface is use to communicate kit with the Matlab.
The Visual Dsp++ will help us to do the source code for Blackfin 532 to implement the watermarking algorithm and to debug.
The MatLab R2010a will help us to see images on GUI Window from processor uart through pc.
This Figure shows the implementation of Image Watermarking algorithm in this project
The program has written as per the above explanation. This project you can implement in directly to BF532 kit. This programming concept you can use any one of the BF533/32/31 Blackfin processor with good SDRAM capacity to handle huge datas, such a general concept implemented.
This project source code is available at our website. User can download that project once you registered. For more queries, please contact through forum.
This Project Video file is available at the following path:
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