A new image fusion scheme based on wavelet transform is proposed in this paper. Firstly, the image is decomposed into high-frequency images and low frequency images with wavelet transform, then the spatial frequency and the contrast of the low-frequency image are measured to determine the fused low frequency image, and to the high-frequency image, we select the high- frequency coefficient based on the absolute value maximum principal and verify the consistency of these coefficients. Finally, the image can be reconstructed with Mallat algorithm.
The experimental results show that the scheme can preserve all useful information from primitive images and the clarity and the contrast of the fused image are improved. The presented scheme is verified to be effective for the image fusion.
The ADSP-BF533/32/31 processors are enhanced members of the Blackfin processor family that offer significantly higher performance and lower power than previous Blackfin processors while retaining their ease-of-use and code compatibility benefits, processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory.
The Blackfin processor core architecture combines a dual MAC signal processing engine, an orthogonal RISC-like microprocessor instruction set, flexible Single Instruction, Multiple Data (SIMD) capabilities, and multimedia features into a single instruction set architecture. Blackfin products feature dynamic power management. The ability to vary both the voltage and frequency of operation optimizes the power consumption profile to the specific task.
The BLACKFIN EVALUATION BOARD is specially designed for developers in dsp field as well as beginners. The BF532 kit is designed in such way that all the possible features of the DSP will be easily used by everyone. The kit supports in VisualDsp++5.0 and later.
The Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection.
The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.
The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.
Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only.
Image fusion is to integrate the information of two or more source images in order to obtain the more accurate, comprehensive and reliable description of the same scene.
As there are information redundancy and complementarily among multiple images of the same scene obtained by different image sensors, it is particularly important to synthesize a new image by image fusion technology, which can provide more abundant information than original image. Image fusion is widely used in military, remote sensing, computer vision and medical image processing, etc.
Image fusion is a process of combining images,obtained by sensors of different wavelengths simultaneously viewing the same scene, to form a composite image. The composite image is formed to improve image content and to make it easier for the user to detect, recognize, and identify targets and increase his situational awareness.
The following are playing a major in our project:
The Blackfin Evaluation Board has 128Mbit SDRAM interfaced in BF532 kit. This interface will use to store a huge data (pixel) .
The RS232 9 pin serial communication is interfaced through UART Serial Interface peripheral. This interface is use to communicate kit with the Matlab.
The Visual Dsp++ will help us to do the source code for Blackfin 532 to implement the Image Fusion algorithm and to debug.
The MatLab R2010a will help us to see images on GUI Window from processor uart through pc.
This Figure shows the implementation of Image Fusion algorithm in this project
The program has written as per the above explanation. This project you can implement in directly to BF532 kit. This programming concept you can use any one of the BF533/32/31 Blackfin processor with good SDRAM capacity to handle huge datas, such a general concept implemented.
This project source code is available at our website. User can download that project once you registered. For more queries, please contact through forum.
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