In an image transmission process, there are a lot of noises which are usually divided into three groups: Gaussian noise, balanced noise and impulse noise. Impulse noise displays as random white or black dots on an image. It corrupts the image and seriously affects the visual effects.
Therefore, the impulse noise reduction has important significance to image processing. The median filter is a nonlinear filter and it has widely used in digital image processing because of its demonstrated ability to reduce impulse noise without blurring edges.
It is a neighborhood operation and its noise-reducing effect depends on the size and shape of the filter mask; the algorithm complexity of it mainly depends on how to obtain the median. In order to improve the noise-reducing effect of the median filter, scholars proposed some improved methods to the standard median filter.
To solve the contradiction between the noise reducing effect and the time complexity of the standard median filter algorithm, the paper proposed an improved median filter algorithm combined with average filtering.
According to the correlation of the image, the algorithm adaptively resizes the filter mask according to noise levels of the mask.
According to the sorting results of the selected pixel values in the neighborhood, the algorithm uses the median to replace the original pixel.
Experimental results show that the improved algorithm can effectively reduce time complexity and has better noise-reducing effect than the standard median filter algorithm. It has a good application prospect in image processing.
The ADSP-BF533/32/31 processors are enhanced members of the Blackfin processor family that offer significantly higher performance and lower power than previous Blackfin processors while retaining their ease-of-use and code compatibility benefits, processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory.
The Blackfin processor core architecture combines a dual MAC signal processing engine, an orthogonal RISC-like microprocessor instruction set, flexible Single Instruction, Multiple Data (SIMD) capabilities, and multimedia features into a single instruction set architecture. Blackfin products feature dynamic power management. The ability to vary both the voltage and frequency of operation optimizes the power consumption profile to the specific task.
The BLACKFIN EVALUATION BOARD is specially designed for developers in dsp field as well as beginners. The BF532 kit is designed in such way that all the possible features of the DSP will be easily used by everyone. The kit supports in VisualDsp++5.0 and later.
The Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection.
The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.
The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.
Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only.
Image denoising refers to the recovery of a digital image that has been contaminated by additive white Gaussian noise (AWGN). Image denoising is an important image processing task, both as a process itself, and as a component in other processes. Very many ways to denoise an image or a set of data exists.
The main property of a good image denoising model is that it will remove noise while preserving edges. Traditionally, linear models have been used. One common approach is to use a Gaussian filter, or equivalently solving the heat-equation with the noisy image as input-data, i.e. a linear, 2nd order PDE-model. For some purposes this kind of denoising is adequate.
One big advantage of linear noise removal models is the speed. But a drawback of the linear models is that they are not able to preserve edges in a good manner: edges, which are recognized as discontinuities in the image, are smeared out. Nonlinear models on the other hand can handle edges in a much better way than linear models can. One popular model for nonlinear image denoising is the Total Variation (TV)-filter. This filter is very good at preserving edges, but smoothly varying regions in the input image are transformed into piecewise constant regions in the output image.
The following are playing a major in our project:
The Blackfin Evaluation Board has 128Mbit SDRAM interfaced in BF532 kit. This interface will use to store a huge data (pixel) .
The RS232 9 pin serial communication is interfaced through UART Serial Interface peripheral. This interface is use to communicate kit with the Matlab.
The Visual Dsp++ will help us to do the source code for Blackfin 532 to implement the Image Denoising algorithm and to debug.
The MatLab R2010a will help us to see images on GUI Window from processor uart through pc.
This Figure shows the implementation of Image Denoising algorithm in this project
The program has written as per the above explanation. This project you can implement in directly to BF532 kit. This programming concept you can use any one of the BF533/32/31 Blackfin processor with good SDRAM capacity to handle huge datas, such a general concept implemented.
This project source code is available at our website. User can download that project once you registered. For more queries, please contact through forum.
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