Implementation of Image Compression in BF532 DSP Kit

Implementation of Image Compression in BF532 DSP Kit

Tags: Image compression using dsp processor, image processing project using dsp processor,wavelet based image compression using bf532 dsp,c source code for image compression,
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Image compression means reducing the volume of data for representing an image. The main aim of image compression is to reduce both spatial and spectral redundancy to store or transmit data in a proper manner. After the compression of an image, it is reconstructed at the receiver to reproduce the original image. Various compression techniques are used for this purpose. In lossless image compression, some form of entropy coding is used, while in lossy compression transform coding and predictive coding is used.

With the inherent features of wavelet transform, it provides multi-resolution functionality and better compression performance at very low bit-rate compared with the previous JPEG standard. For this purpose many wavelet based algorithms have been implemented. For constructing biorthogonal wavelets, lifting scheme is a new method. In this paper, a new lossless image compression method is proposed.

For continuous and discrete time cases, wavelet transform and wavelet packet transform has emerged as popular techniques. While integer wavelet using the lifting scheme significantly reduces the computation time, we propose a completely new approach for further speeding up the computation. First, wavelet packet transforms (WPT) and lifting scheme (LS) are described.

Then an application of the LS to WPT is presented which leads to the generation of Integer wavelet packet transform (IWPT). The proposed method, Integer Wavelet Packet Transform (IWPT) yields a representation which can be lossless, as it maps an integer valued sequence onto the integer valued coefficients.

The idea of Wavelet Packet Tree is used to transform the still and color images. IWPT tree can be built by iterating the single wavelet decomposition step on both the low-pass and high-pass branches, with rounding off in order to achieve the integer transforms.

Thus, the proposed method provides good compression ratio.


The ADSP-BF533/32/31 processors are enhanced members of the Blackfin processor family that offer significantly higher performance and lower power than previous Blackfin processors while retaining their ease-of-use and code compatibility benefits, processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory.

The Blackfin processor core architecture combines a dual MAC signal processing engine, an orthogonal RISC-like microprocessor instruction set, flexible Single Instruction, Multiple Data (SIMD) capabilities, and multimedia features into a single instruction set architecture. Blackfin products feature dynamic power management. The ability to vary both the voltage and frequency of operation optimizes the power consumption profile to the specific task.

The BLACKFIN EVALUATION BOARD is specially designed for developers in dsp field as well as beginners. The BF532 kit is designed in such way that all the possible features of the DSP will be easily used by everyone. The kit supports in VisualDsp++5.0 and later.





The Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.

Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.

The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection.

The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.

The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.

The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.

Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only.


The objective of image compression is to reduce irrelevance and redundancy of the image data in order to be able to store or transmit data in an efficient form.

Image compression is minimizing the size in bytes of a graphics file without degrading the quality of the image to an unacceptable level. The reduction in file size allows more images to be stored in a given amount of disk or memory space. It also reduces the time required for images to be sent over the Internet or downloaded from Web pages.

There are several different ways in which image files can be compressed. For Internet use, the two most common compressed graphic image formats are the JPEG format and the GIF format. The JPEG method is more often used for photographs, while the GIF method is commonly used for line art and other images in which geometric shapes are relatively simple.

Other techniques for image compression include the use of fractals and wavelets. These methods have not gained widespread acceptance for use on the Internet as of this writing. However, both methods offer promise because they offer higher compression ratios than the JPEG or GIF methods for some types of images. Another new method that may in time replace the GIF format is the PNG format.

A text file or program can be compressed without the introduction of errors, but only up to a certain extent. This is called lossless compression. Beyond this point, errors are introduced. In text and program files, it is crucial that compression be lossless because a single error can seriously damage the meaning of a text file, or cause a program not to run.

In image compression, a small loss in quality is usually not noticeable. There is no "critical point" up to which compression works perfectly, but beyond which it becomes impossible. When there is some tolerance for loss, the compression factor can be greater than it can when there is no loss tolerance. For this reason, graphic images can be compressed more than text files or programs.


  • Transmission Application
  • Storage Application


The following are playing a major in our project:

  • BF532 KIT with 128Mbit SDRAM, 1Mbyte FLASH & UART
  • Visual Dsp++

The Blackfin Evaluation Board has 128Mbit SDRAM interfaced in BF532 kit. This interface will use to store a huge data (pixel) .

The RS232 9 pin serial communication is interfaced through UART Serial Interface peripheral. This interface is use to communicate kit with the Matlab.

The Visual Dsp++ will help us to do the source code for Blackfin 532 to implement the Image Compression algorithm and to debug.

The MatLab R2010a will help us to see images on GUI Window from processor uart through pc.



This Figure shows the implementation of Image Compression algorithm in this project




The program has written as per the above explanation. This project you can implement in directly to BF532 kit. This programming concept you can use any one of the BF533/32/31 Blackfin processor with good SDRAM capacity to handle huge datas, such a general concept implemented.

This project source code is available at our website. User can download that project once you registered. For more queries, please contact through forum.

This Project Video file is available at the following path:

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