The proliferation of digital data in their various formats has attracted a special interest from researchers to ensure their security. Techniques such as encryption and watermarking are already used in this regard. However, the need for new techniques and new algorithms to counter constantly-changing malicious attempts to the integrity of digital data has become a necessity in today’s digital era. Steganography, which literary means”covered writing” has drawn more attention in the last few years. Its primary goal is to hide the fact that a communication is taking place between two parties. The sender embeds secret data of any type using a key in a digital cover file to produce a stego file, in such a way that an observer cannot detect the existence of the hidden message.
At the other end, the receiver processes the received stego-file to extract the hidden message. An example of audio steganography is depicted in Fig. 1 where the cover file being used is a digital audio signal.
An obvious application is a covert communication using innocuous cover audio signal, such as telephone or video conference conversations lately, novel and versatile audio steganographic methods have been proposed.
A perfect audio Steganographic technique aim at embedding data in an imperceptible, robust and secure way and then extracting it by authorized people. Hence, up to date the main challenge in digital audio steganography is to obtain robust high capacity steganographic systems.
Leaning towards designing a system that ensures high capacity or robustness and security of embedded data has led to great diversity in the existing steganographic techniques. In this paper, we present a current state of art literature in digital audio steganographic techniques. We explore their potentials and limitations to ensure secure communication. A comparison and an evaluation for the reviewed techniques are also presented in this paper.
The ADSP-BF533/32/31 processors are enhanced members of the Blackfin processor family that offer significantly higher performance and lower power than previous Blackfin processors while retaining their ease-of-use and code compatibility benefits, processors are completely code and pin-compatible, differing only with respect to their performance and on-chip memory.
The Blackfin processor core architecture combines a dual MAC signal processing engine, an orthogonal RISC-like microprocessor instruction set, flexible Single Instruction, Multiple Data (SIMD) capabilities, and multimedia features into a single instruction set architecture. Blackfin products feature dynamic power management. The ability to vary both the voltage and frequency of operation optimizes the power consumption profile to the specific task.
The BLACKFIN EVALUATION BOARD is specially designed for developers in dsp field as well as beginners. The BF532 kit is designed in such way that all the possible features of the DSP will be easily used by everyone. The kit supports in VisualDsp++5.0 and later.
The Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter. The computation units process 8-bit, 16-bit, or 32-bit data from the register file. The compute register file contains eight 32-bit registers. When performing compute operations on 16-bit operand data, the register file operates as 16 independent 16-bit registers. All operands for compute operations come from the multiported register file and instruction constant fields.
Each MAC can perform a 16-bit by 16-bit multiply in each cycle, accumulating the results into the 40-bit accumulators. Signed and unsigned formats, rounding, and saturation are supported.
The ALUs perform a traditional set of arithmetic and logical operations on 16-bit or 32-bit data. In addition, many special instructions are included to accelerate various signal processing tasks. These include bit operations such as field extract and population count, modulo 232 multiply, divide primitives, saturation and rounding, and sign/exponent detection.
The set of video instructions includes byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions.
The 40-bit shifter can perform shifts and rotates and is used to support normalization, field extract, and field deposit instructions.
The program sequencer controls the flow of instruction execution, including instruction alignment and decoding. For program flow control, the sequencer supports PC relative and indirect conditional jumps (with static branch prediction), and subroutine calls. Hardware is provided to support zero-overhead looping. The architecture is fully interlocked, meaning that the programmer need not manage the pipeline when executing instructions with data dependencies.
Blackfin processors support a modified Harvard architecture in combination with a hierarchical memory structure. Level 1 (L1) memories are those that typically operate at the full processor speed with little or no latency. At the L1 level, the instruction memory holds instructions only.
Steganography is the art and science of writing hidden messages in such a way that no one, apart from the sender and intended recipient, suspects the existence of the message, a form of security through obscurity. Generally, messages will appear to be something else: images, articles, shopping lists, or some other covertext and, classically, the hidden message may be in invisible ink between the visible lines of a private letter.
The advantage of steganography over cryptography alone is that messages do not attract attention to themselves. Plainly visible encrypted messages—no matter how unbreakable—will arouse suspicion, and may in themselves be incriminating in countries where encryption is illegal.
Therefore, whereas cryptography protects the contents of a message, steganography can be said to protect both messages and communicating parties. Steganography includes the concealment of information within computer files.
In digital steganography, electronic communications may include steganographic coding inside of a transport layer, such as a document file, image file, program or protocol.
The following are playing a major in our project:
The Blackfin Evaluation Board has 128Mbit SDRAM interfaced in BF532 kit. This interface will use to store a huge data (pixel) .
The RS232 9 pin serial communication is interfaced through UART Serial Interface peripheral. This interface is use to communicate kit with the Matlab.
The Visual Dsp++ will help us to do the source code for Blackfin 532 to implement the Audio Steganography algorithm and to debug.
The MatLab R2010a will help us to see images on GUI Window from processor uart through pc.
This Figure shows the implementation of Audio Steganography algorithm in this project
The program has written as per the above explanation. This project you can implement in directly to BF532 kit. This programming concept you can use any one of the BF533/32/31 Blackfin processor with good SDRAM capacity to handle huge datas, such a general concept implemented.
This project source code is available at our website. User can download that project once you registered. For more queries, please contact through forum.
This Project Video file is available at the following path:
we respect your privacy.