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The inverter plays a vital role in Uninterrupted Power Supply (UPS). It is used to convert the direct current (DC) to alternating Current (AC) of required voltage.


The single phase parallel inverter circuit consists of two SCRs T1 and T2, an inductor L, an output transformer and a commutating capacitor C. The output voltage and current are Vo and Io respectively. The function of L is to make the source current constant. During the working of this inverter, capacitor C comes in parallel with the load via the transformer. So it is called a parallel inverter.

The operation of this inverter can be explained in the following modes.

Mode I

In this mode, SCR T1 is conducting and a current flow in the upper half of primary winding. SCR T2 is OFF. As a result an emf Vs is induced across upper as well as lower half of the primary winding.

In other words total voltage across primary winding is 2 Vs. Now the capacitor C charges to a voltage of 2Vs with upper plate as positive.

Mode I

Mode II

At time to, T2 is turned ON by applying a trigger pulse to its gate. At this time t=0, capacitor voltage 2Vs appears as a reverse bias across T1, it is therefore turned OFF. A current Io begins to flow through T2 and lower half of primary winding. Now the capacitor has charged (upper plate as negative) from +2Vs to -2Vs at time t=t1. Load voltage also changes from Vs at t=0 to –Vs at t=t1.

Mode III

When capacitor has charged to –Vs, T1 may be tuned ON at any time. When T1 is triggered, capacitor voltage 2Vs applies a reverse bias across T2, it is therefore turned OFF. After T2 is OFF, capacitor starts discharging, and charged to the opposite direction, the upper plate as positive.

Paralleled Commutated Inverter

Fig 1: is a schematic of the classical parallel commutated square wave inverter bridge. It is being included here for illustrative purposes since most other circuits utilize this circuit or a variation there of. The waveform generated and supplied to the load is basically a square wave having a peak to peak amplitude of twice the DC supply voltage and a period that is determined by the relate at which SCR ‰s 1 through 4 are gated on. The SCR ‰s are turned on in pairs by simultaneously applying signals to the gate terminals of SCR ‰s 1 and 4 or SCR ‰s 2 and 3. If SCR ‰s 1 and 4 happen to be the first two switched on a current will flow from the positive terminal of the source through negative terminal of the source. This will establish a left to right, plus to minus voltage relationship on the load.

Simultaneously, the left terminal of capacitor C1 will be charged positively with respect to the right negative terminal. The steady-state load current through the various components is determined nearly completely by the impedance of the load. Chokes 1 and 2 and SCR‰s 1 and 4 present very low steady-state drops and therefore nearly all the source voltage appears across the load. Conduction of SCR ‰s 1 and 4 will continue to the end of the half cycle, at which point the gates are removed from SCR‰s 1 and 4 remain in conduction along with SCR‰s 2 and 3 that have now been turned on. If it were not for chokes 1 and 2, the action of turning on the second set of SCR‰s would place very low impedance and therefore momentarily prevent the source from being short-circuited.

Capacitor C1 now discharges with a current which flows into the cathode of SCR 1 through SCR 2 in a forward direction back to the negative terminal of the capacitor. This direction of current flow causes SCR 1 to become non-conductive provided that the reverse current through the SCR is of sufficient duration for the SCR to again become blocking. C1 simultaneously discharges through SCR 3 in a forward direction and through SCR 4 in a reverse direction. This will cause SCR 4 to become non-conductive just the same SCR 1. This entire sequence is referred to as commutation and typically in a modern inverter would occur in a period of time less than 50 microseconds. During this interval, chokes 1and 2 must have sufficient transient impedance to prevent a significant increase in current from the DC source.

Diodes 1, 2, 3 and 4 serve two functions. The first is to return any stored energy that may be "kicked back" from the load to the source. They also serve to prevent the choke from generating a high transient voltage immediately after commutation.

Paralleled Commutated Inverter

Fig 1: Common Inverter Bridge (Parallel Commutated Type)

Using the present example, when all four SCR‰s are on (just after the second two are gated on), the current through the choke does increase somewhat, but must drip back to a new lower valve after SCR‰s 1 and 4 have assumed the blocking state.

When the current through choke 1 is reduced, a voltage is generated in a negative to positive from the top to the bottom of the choke that will cause current to flow through SCR 2 and back through diode D2 to the now negative terminal of choke CH1. A similar action takes place on choke CH2, except now diode D3 and SCR 3 form the conductive path. SCR‰s and 3 remain conductive until the end of the half cycle, at which time SCR‰s1 and 4 are gated on to repeat the entire process once again.

This circuit may be employed directly to a very limited application where the load will tolerate the harmonic content of the square wave output. Forward load current must be limited to insure that the stored energy in C1 is sufficient to be commutate the SCR‰s. When the square wave inverter of this type is employed, no current-limit exists and therefore overloads even those of a transient nature, may cause a commutation failure which results in total loss of the output voltage. This basic circuit is rugged and reliable and with modifications it is being used in a great many practical situations, some of which will be discussed in this paper.