The dsPIC microcontroller is a part of Microchip's 16-Bit microcontroller family. The architecture of dsPIC or Digital Signal Controller is same as the architecture with PIC 16-bit family, with additional blocks of Digital Signal Processing. This power up the standard Microcontroller with powerful mathematical processor required for a Digital Signal Processor. This gives a tremendous amount of functionality into one single chip.
The 16-bit dsPIC30F Digital Signal Controller (DSC) is Microchip’s newest and most advanced processor family. The dsPIC30F is an advanced 16-bit processor that offers true DSP capability with the fundamental real-time control capabilities of a microcontroller. Prioritized interrupts, extensive built-in peripherals and power management features are combined with a full-featured DSP engine.
Dual 40-bit accumulators, single-cycle 16x16 MAC, 40-bit barrel shifter, dual-operand fetches and zero-overhead looping are among the features that make this a very capable DSC.
The dsPIC30F device family employs a powerful 16-bit architecture that seamlessly integrates the control features of a microprocessor (MCU) with the computational capabilities of a digital signal processor (DSP). The resulting functionality is ideal for applications that rely on high-speed, repetitive computations as well as control.
The DSP engine, dual 40-bit accumulators, hardware support for division operations, barrel shifter, 17 x 17 multiplier, a large array of 16-bit working registers and a wide variety of data addressing modes together provide the dsPIC30F CPU with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the dsPIC30F devices suitable for control applications.
Reliable, field programmable Flash program memory and data EEPROM ensure scalability of applications that use dsPIC30F devices.
The main Features of dsPIC30F is,
The dsPIC30F devices can operate at instruction execution speeds up to 30 MIPS. All the devices use Flash memory, and can operate in the extended temperature range up to 125 degrees Centigrade.
They are available in two speed categories: a 20 MIPS version and a 30 MIPS version. A wide range of device packaging options are supported for each device, from the tiny 28-pin QFN packages to the larger Dual Inline packages and large-pin-count Quad Flat Pack packages.
The dsPIC30F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word, with a variable length op code field.
The program counter (PC) is 24-bits wide and addresses up to 4M x 24 bits of user program memory space. A single cycle instruction pre-fetch mechanism is used to help maintain throughput and provides predictable execution.
All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
The dsPIC30F devices have sixteen 16-bit working registers in programmer’s model. Each of the working registers can act as a data, address, or address offset register. The 16th working register (W15) operates as a software stack pointer for interrupts and calls.
The dsPIC30F instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many Addressing modes and was designed for optimum C compiler efficiency.
The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit (AGU). The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space. Certain DSP instructions operate through the X and Y AGUs to support dual operand reads which splits the data address space into two parts. The X and Y data space boundary is device specific.
The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register.
The program to data space mapping feature lets any instruction access program space as if it were data space. Furthermore, RAM may be connected to the program memory bus on devices with an external bus and used to extend the internal data RAM.
Overhead free circular buffers (modulo addressing) are supported in both X and Y addresses spaces. Modulo addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports bit-reverse addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms.
The CPU supports Inherent (no operand), Relative, Literal, Memory Direct, and Register Direct and Register Indirect Addressing modes. Each instruction is associated with a predefined Addressing mode group depending upon its functional requirements. As many as 6 Addressing modes are supported for each instruction.
For most instructions, the dsPIC30F is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle.
As a result, 3 operand instructions can be supported, allowing A+B=C operations to be executed in a single cycle. The DSP engine features a high speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bi-directional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up to 15 bits right, or up to 16 bits left, in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance.
The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers. This requires that the data space be split for these instructions and linear for all others.
This is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.
The dsPIC30F has a vectored exception scheme with up to 8 sources of non-mask able traps and 54 interrupt sources. Each interrupt source can be assigned to one of seven priority levels.
In a pure Harvard architecture has separate memory areas for program instructions and data. These two busses (instruction & Data) are completely separate, with no way to pass data between them. The CPU fetches instructions on the program memory bus and fetches data on data memory bus.
The dsPIC DSC employs a modified Harvard architecture. A modified Harvard architecture in dsPIC has separate program memory and two data memory buses. This allows the processor to simultaneously fetch both an instruction and the data (sampled data and coefficient).
A Harvard Architecture allows fetching single data value in one cycle. In the digital signal processing applications, it requires to fetch the data fast for faster processing. For signal processing to data values are required sampled data and a coefficient by which it will be multiplied. To achieve this, the modified Harvard architecture supports three busses: one to fetch the instructions (the program memory bus) and two to fetch associated data values.
This allows true single cycle operation, effectively doubling system throughput when compared to a pure Harvard architecture running at the same speed.
The dsPIC30F CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, including significant support for DSP. The CPU has a 24-bit instruction word, with a variable length op code field. The program counter (PC) is 23- bits wide and addresses up to 4M x 24 bits of user program memory space.
A single cycle instruction pre-fetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions.
Overhead free program loop constructs are supported using the DO and REPEAT instructions, both of which are interruptible at any point.
The dsPIC30F devices have sixteen 16-bit working registers in the programmer’s model.
Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software stack pointer for interrupts and calls.
The dsPIC30F instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit. The instruction set includes many addressing modes and is designed for optimum C compiler efficiency.
The data space can be addressed as 32K words or 64 Kbytes and is split into two blocks, referred to as X and Y data memory. Each memory block has its own independent Address Generation Unit. The MCU class of instructions operates solely through the X memory AGU, which accesses the entire memory map as one linear data space.
Certain DSP instructions operate through the X and Y AGUs to support dual operand reads which splits the data address space into two parts. The X and Y data space boundary is device specific.
The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program-to-data-space mapping feature lets any instruction access program space as if it were data space.
Overhead free circular buffers are supported in both X and Y addresses spaces. Modulo addressing removes the software boundary checking overhead for DSP algorithms. Furthermore, the X AGU circular addressing can be used with any of the MCU class of instructions. The X AGU also supports bit-reversed addressing to greatly simplify input or output data reordering for radix-2 FFT algorithms.
The CPU supports Inherent (no operand), Relative, Literal, Memory Direct, Register Direct and Register Indirect addressing modes. Each instruction is associated with a predefined addressing mode group depending upon its functional requirements. As many as 6 addressing modes are supported for each instruction.
For most instructions, the dsPIC30F is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle.
The DSP engine features a high speed, 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up to 16 bits right or left, in a single cycle.
The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real time performance.
The MAC instruction and other associated instructions can concurrently fetch two data operands from memory while multiplying two W registers and accumulating and optionally saturating the result in the same cycle.
This instruction functionality requires that the RAM memory data space be split for these instructions and linear for all others. Data space partitioning is achieved in a transparent and flexible manner through dedicating certain working registers to each address space.
The dsPIC30F features a 17-bit by 17-bit single-cycle multiplier that is shared by both the MCU ALU and DSP Engine. The multiplier can perform signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication not only allows you to perform mixed-sign multiplication, it also achieves accurate results for special operations such as (-1.0) x (-1.0).
The dsPIC30F supports 16/16 and 32/16 divide operations, both fractional and integer. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A 40-bit barrel shifter is used to perform up to a 16-bit left or right shift, in a single cycle. The barrel shifter can be used by both MCU and DSP instructions.
The dsPIC30F has a vectored exception scheme with up to 8 sources of non-mask able traps and 54 interrupt sources. Each interrupt source can be assigned to one of seven priority levels.
In addition to extensive DSP capability, the CPU architecture possesses several features,
The DSP engine consists of a high-speed, single-cycle, 17-bit x 17-bit multiplier, a barrel shifter and a 40-bit adder/subtraction with two target accumulators, rounded saturation logic, all of which enable efficient execution of computationally intensive DSP algorithms.
The 17-bit x 17-bit multiplier is also utilized for MCU based multiply instructions. The DSP engine also has the capability to perform inherent accumulator-to-accumulator operations, which require no additional data. These instructions are ADD, SUB and NEG.
This feature greatly simplifies basic arithmetic operations on 32-bit or 40-bit data.
The 17 x 17-bit multiplier is capable of signed or unsigned operation. It can suitably scale its output to support either 1.31 fractional (Q31) or 32-bit integer results, thereby diminishing the need to manually post-process multiplication results for fractional data.
The data accumulators have a 40-bit adder/subtraction with automatic sign-extension logic. It can select one of two accumulators (A or B) as its pre-accumulation source and post-accumulation destination. For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation.
The adder/subtraction generates overflow status bits SA/SB and OA/OB, which are latched and reflected in the Status Register and can also optionally generate an Arithmetic Error Trap:
The adder has an additional saturation block that controls accumulator data saturation, if selected. It uses the result of the adder, the overflow status bits described above, and the user-configured control bits to determine when to saturate and to what value to saturate (a 40-bit or a 32-bit value).
In addition to adder/subtraction saturation, writes to data space can also be saturated, but without affecting the contents of source accumulator.
The rounding logic performs a conventional (biased) or convergent (unbiased) data rounding function during an accumulator write (store). The Round mode is user selectable.
Rounding generates a 16-bit, 1.15 data value, which is passed to the data space write saturation logic. Data space write saturation ensures that the data in the accumulator is written back accurately even when rounding is performed. If rounding is not indicated by the instruction, a truncated 1.15 data value is stored and the LS Word is simply discarded.
The dsPIC30F has four processor exceptions (traps) and up to 45 sources of interrupts, which must be arbitrated based on a priority scheme.
The processor core is responsible for reading the Interrupt Vector Table (IVT) and transferring the address contained of the interrupt vector to the program counter.
The Interrupt Vector Table (IVT) and Alternate Interrupt Vector Table (AIVT) are placed near the beginning of program memory (0x000004) for ease of debugging.
The interrupt controller hardware pre-processes the interrupts before they are presented to the CPU. The interrupts and traps are enabled, prioritized and controlled using centralized special function registers.
Each individual interrupt source has its own vector address and can be individually enabled and prioritized in user software. Each interrupt source also has its own status flag.
This independent control and monitoring of the interrupt eliminates the need to poll various status flags to determine the interrupt source contains information about the interrupt vector.
Certain interrupts have specialized control bits for features like edge or level triggered interrupts, interrupt-on-change, etc. Control of these features remains within the peripheral module, which generates the interrupt.
The special DISI instruction can be used to disable the processing of interrupts of priorities 6 and lower for a certain number of instruction cycles, during which the DISI bit remains set.
Each interrupt source can be user assigned to one of 8 priority levels, 1 through 7. Levels 7 and 1 represent the highest and lowest mask able priorities, respectively. A priority level of 0 disables the interrupt.
Since more than one interrupt request source may be assigned to a user specified priority level, a means is provided to assign priority within a given level. This method is called “Natural Order Priority”.
The Natural Order Priority of an interrupt is numerically identical to its Vector Number. The natural order priority scheme has 0 as the highest priority and 53 as the lowest priority.
The ability for the user to assign every interrupt to one of eight priority levels implies that the user can assign a very high overall priority level to an interrupt with a low natural order priority, thereby providing much flexibility in designing applications that use a large number of peripherals.
Interrupts, by default, are nest able. Any ISR that is in progress may be interrupted by another source of interrupt with a higher user assigned priority level. Interrupt nesting may be optionally disabled by setting the NSTDIS control bit (INTCON1<15>). When the NSTDIS control bit is set, all interrupts in progress will force the CPU priority to level 7 by setting IPL<2:0> = 111.
This action will effectively mask all other sources of interrupt until a RETFIE instruction is executed.
When interrupt nesting is disabled, the user assigned interrupt priority levels will have no effect, except to resolve conflicts between simultaneous pending interrupts.
The IPL<2:0> bits become read only when interrupt nesting is disabled. This prevents the user software from setting IPL<2:0> to a lower value, which would effectively re-enable interrupt nesting.
Traps can be considered as non-mask able, nest able interrupts that adhere to a fixed priority structure. Traps are intended to provide the user a means to correct erroneous operation during debug and when operating within the application. If the user does not intend to take corrective action in the event of a trap error condition, these vectors must be loaded with the address of a software routine that will reset the device.
Otherwise, the trap vector is programmed with the address of a service routine that will correct the trap condition. The dsPIC30F has four implemented sources of non-mask able traps:
Many of these trap conditions can only be detected when they happen. Consequently, the instruction that caused the trap is allowed to complete before exception processing begins. Therefore, the user may have to correct the action of the instruction that caused the trap.
Each trap source has a fixed priority as defined by its position in the IVT. An oscillator failure trap has the highest priority, while an arithmetic error trap has the lowest priority.
Any available interrupt can be manually generated by user software simply by enabling the interrupt and then setting the interrupt flag bit when required.
System management services provided by the dsPIC30F device family include:
When a supply voltage is applied to the device, a Power-On Reset is generated. A new Power-On Reset event is generated if the supply voltage falls below the device threshold voltage (VPOR). An internal POR pulse is generated when the rising supply voltage crosses the POR circuit threshold voltage.
The BOR (Brown-out Reset) module is based on an internal voltage reference circuit. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs.
Brown-out conditions are generally caused by glitches on the AC mains, i.e., missing portions of the AC cycle waveform due to bad power transmission lines or voltage sags due to excessive current draw when a large inductive load is turned on.
The BOR module allows selection of one of the following voltage trip points:
A BOR generates a Reset pulse, which resets the device.
There are three primary clock oscillators: XTL, XT and HS. The XTL oscillator is designed for crystals or ceramic resonators in the range of 200 kHz to 4MHz.
The XT oscillator is designed for crystals and ceramic resonators in the range of 4 to 10MHz. The HS (High- Speed) oscillator is for crystals in the 10 to 25 MHz range. These oscillators use the OSC1 and OSC2 pins.
The secondary (LP) oscillator is designed for low power and uses a 32 kHz crystal or ceramic resonator. The LP oscillator uses the SOSC1 and SOSC2 pins. The FRC (Fast RC) internal oscillator runs at a nominal 8MHz. The user software can tune the FRC frequency. The LPRC (Low Power RC) internal oscillator is connected to the Watchdog Timer, and it runs at a nominal 512 kHz. The External RC (ERC) oscillator uses an external resistor and capacitor connected to the OSC1 pin. Frequency of operation is up to 4MHz.
The OSC1 pin can also be used as an input from an external clock source; this mode is called “EC”.
The dsPIC30F oscillator system provides:
There are two internal timers that offer necessary delays on power-up. One is the Power-up Timer (PWRT), which provides a delay on power-up only. The PWRT keeps the part in Reset while the power supply stabilizes. The other is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable. With these two timers on-chip, most applications need no external Reset circuitry.
An Oscillator Start-up Timer is included to ensure that a crystal oscillator has started and stabilized. The OST is a simple 10-bit counter that counts 1024 TOSC cycles before releasing the oscillator clock to the rest of the system.
The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer that runs off an on-chip RC oscillator, requiring no external component. The WDT timer continues to operate even if the main processor clock (e.g., the crystal oscillator) fails.
The Watchdog Timer can be “Enabled” or “Disabled” either through a configuration bit (FWDTEN) in the configuration register or through an SFR bit (SWDTEN). If enabled, the WDT increments until it overflows or “times out”. A WDT time-out forces a device Reset.
The Fail-Safe Clock Monitor allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal oscillator runs at all times and is not subject to control by the watchdog timer.
In the event of an oscillator failure, the FSCM generates a Clock Failure Trap event and switches the system clock over to the FRC oscillator. The application program then can either attempt to restart the oscillator, or execute a controlled shutdown.
The Reset system combines all Reset sources and controls the device Master Reset signal. Device Reset sources include:
The organization of memory and the mode of its use are called the memory model.
Understanding the memory model is essential for programming. The memory is divided into the program memory and data memory. The program memory is further divided into the user program space and the user configuration space.
The data memory is the space of memory locations used by a program for saving different data required for the program execution. The size of the memory space is different for different members of the dsPIC30F family.
The dsPIC30F microcontrollers have 4M 24-bit (3 bytes) program memory address space. This does not mean that the size of the memory is 12MB (3x4M=12MB), but that is can generate 4M (4x220) different addresses.
The size of the program memory of a dsPIC30F4013 device is 16K words, i.e. 3x16K=48KB. A program can have 16K instructions less the number of auxiliary locations.
The first two locations are reserved for defining the beginning of a program. The execution of a program starts from the program memory is accessible only via even addresses. An attempt to read an odd address will result in CPU trap and device reset.
The PC increments by 2 with the LSB set to ‘0’ to provide compatibility with data space addressing. Sequential instruction words are addressed in the 4M program memory space by PC<22:1>. Each instruction word is 24-bits wide.
The LSB of the program memory address is reserved as a byte select bit for program memory accesses from data space that use Program Space Visibility or table instructions. For instruction fetches via the PC, the byte select bit is not required. Therefore, PC<0> is always set to ‘0’.
There are two methods by which data can be transferred between the program memory and data memory spaces: via special table instructions or through the remapping of a 32-Kbyte program space page into the upper half of data space.
The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the LSB Word of any address within program space without going through data space, which is preferable for some applications. The TBLRDH and TBLWTH instructions are the only method whereby the upper 8-bits of a program word can be accessed as data.
The TBLRDL and TBLWTL instructions are used to access the lower 16 bits of program memory data. The LSB of the W register address is ignored for word-wide table accesses. For byte-wide accesses, the LSB of the W register address determines which byte is read.
The TBLRDH and TBLWTH instructions are used to access the upper 8 bits of the program memory data.
These instructions also support Word or Byte Access modes for orthogonality, but the high byte of the program memory data will always return ‘0’.
It is assumed that for most applications, the high byte (P<23:16>) will not be used for data, making the program memory appear 16-bits wide for data storage. It is recommended that the upper byte of program data be programmed either as a NOP, or as an illegal op code value, to protect the device from accidental execution of stored data. The TBLRDH and TBLWTH instructions are primarily provided for array program/verification purposes and for those applications that require compressed data storage.
The upper 32 Kbytes of the dsPIC30F data memory address space may optionally be mapped into any 16K word program space page.
This mode of operation is called Program Space Visibility (PSV) and provides transparent access of stored constant data from X data space without the need to use special instructions.
Program Space Visibility is enabled by setting the PSV bit (CORCON<2>). When PSV is enabled, each data space address in the upper half of the data memory map will map directly into a program address. The PSV window allows access to the lower 16 bits of the 24-bit program word. The upper 8 bits of the program memory data should be programmed to force an illegal instruction, or a NOP, to maintain machine robustness.
Note that instructions provide the only method of reading the upper 8 bits of each program memory word.
The 15 LSBs of the PSV address are provided by the W register that contains the effective address. The MSB of the W register is not used to form the address.
Instead, the MSB specifies whether to perform a PSV access from program space or a normal access from data memory space.
If a W register effective address of 0x8000 or greater is used, the data access will occur from program memory space when PSV is enabled. All accesses will occur from data memory when the W register effective address is less than 0x8000.
The remaining address bits are provided by the PSVPAG register (PSVPAG<7:0>). The PSVPAG bits are concatenated with the 15 LSBs of the W register, holding the effective address to form a 23-bit program memory address. PSV can only be used to access values in program memory space. Table instructions must be used to access values in the user configuration space.
The LSB of the W register value is used as a byte select bit, which allows instructions using PSV to operate in Byte or Word mode.
The Y data space is located outside of the upper half of data space for most dsPIC30F variants, such that the PSV area will map into X data space. The X and Y mapping will have an effect on how PSV is used in algorithms.
As an example, the PSV mapping can be used to store coefficient data for Finite Impulse Response (FIR) filter algorithms. The FIR filter multiplies each value of a data buffer containing historical filter input data with elements of a data buffer that contains constant filter coefficients.
The FIR algorithm is executed using the MAC instruction within a REPEAT loop. Each iteration of the MAC instruction pre-fetches one historical input value and one coefficient value to be multiplied in the next iteration.
One of the pre-fetched values must be located in X data memory space and the other must be located in Y data memory space.
To satisfy the PSV mapping requirements for the FIR filter algorithm, the user must locate the historical input data in the Y memory space and the filter coefficients in X memory space.
Instructions that use PSV will require two extra instruction cycles to complete execution, except the following instructions that require only one extra cycle to complete execution:
The additional instruction cycles are used to fetch the PSV data on the program memory bus.
Instructions that use PSV within a REPEAT loop eliminate the extra instruction cycle(s) required for the data access from program memory, hence incurring no overhead in execution time.
However, the following iterations of the REPEAT loop will incur an overhead of two instruction cycles to complete execution:
The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory:
1. Run-Time Self Programming (RTSP)
2. In-Circuit Serial Programming™ (ICSP™)
RTSP is accomplished using TBLWT instructions. ICSP is accomplished using the SPI interface and integral boot loader software.
This section describes programming techniques for Flash program memory and data EEPROM memory. The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory:
1. Run-Time Self Programming (RTSP)
2. In-Circuit Serial Programming™ (ICSP™)
RTSP is performed by the user’s software. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP.
The data EEPROM is mapped into the program memory space.
The EEPROM is organized as 16-bit wide memory and the memory size can be up to 2K words (4 Kbytes). The amount of EEPROM is device dependent.
The programming techniques used for the data EEPROM are similar to those used for Flash program memory RTSP.
The key difference between Flash and data EEPROM programming operations is the amount of data that can be programmed or erased during each program/erase cycle.
The following code example shows how to read a word of program memory using the table instructions in Word mode:
In the code example above, the post-increment operator on the read of the low byte causes the address in the working register to increment by one. This sets EA<0> to a ‘1’ for access to the middle byte in the third write instruction. The last post-increment sets W0 back to an even address, pointing to the next program memory location.
Flash and data EEPROM programming operations are controlled using the following Non-Volatile Memory (NVM) control registers:
The NVMCON register is the primary control register for Flash and EEPROM program/erase operations. This register selects Flash or EEPROM memory, whether an erase or program operation will be performed, and is used to start the program or erase cycle.
There are two NVM Address Registers - NVMADRU and NVMADR. These two registers when concatenated form the 24-bit effective address (EA) of the selected row or word for programming operations.
The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA.
The register pair, NVMADRU: NVMADR, capture the EA<23:0> of the last table-write instruction that has been executed and select the row of Flash or EEPROM memory to write/erase.
Although the NVMADRU and NVMADR registers are automatically loaded by the table-write instructions, the user can also directly modify their contents before the programming operation begins. A write to these registers will be required prior to an erase operation, because no table-write instructions are required for any erase operation.
NVMKEY is a write only register that is used to prevent accidental writes/erasures of Flash or EEPROM memory. To start a programming or an erase sequence, the following steps must be taken in the exact order shown:
1. Write 0x55 to NVMKEY.
2. Write 0xAA to NVMKEY.
3. Execute two NOP instructions.
After this sequence, a write will be allowed to the NVMCON register for one instruction cycle.
In most cases, the user will simply need to set the WR bit in the NVMCON register to start the program or erase cycle. Interrupts should be disabled during the unlock sequence.
RTSP allows the user code to modify Flash program memory contents. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions, and the NVM Control registers.
With RTSP, the user may erase program memory, 32 instructions (96 bytes) at a time and can write program memory data, 4 instructions (12 bytes) at a time.
The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. The panel size may vary depending on the dsPIC30F device variant.
Typically, each panel consists of 128 rows, or 4K x 24 instructions. RTSP allows the user to erase one row (32 instructions) at a time and to program 32 instructions at one time.
Each panel of program memory contains write latches that hold 32 instructions of programming data. These latches are not memory mapped. The only way for the user to access the write latches is through the use of table write instructions. Prior to the actual programming operation, the write data must be loaded into the panel write latches with table write instructions. The data to be programmed into the panel is typically loaded in sequential order into the write latches: instruction 0, instruction 1, etc.
The instruction words loaded must always be from an ‘even’ group of four address boundaries (e.g., loading of instructions 3, 4, 5, and 6 is not allowed). Another way of stating this requirement is that the starting program memory address of the four instructions must have the 3 LSB’s equal to ‘0’. All 32 write latches must be written during a programming operation to ensure that any old data held in the latches is overwritten.
The basic sequence for RTSP programming is to setup a table pointer, then do a series of TBLWT instructions to load the write latches. Programming is performed by setting special bits in the NVMCON register. 32 TBLWTL and 32 TBLWTH instructions are required to load the four instructions.
If multiple, discontinuous regions of program memory need to be programmed, the table pointer should be changed for each region and the next set of write latches written.
The entire table writes operations to the Flash program memory take 2 instruction cycles each, because only the table latches are written. The actual programming operation is initiated using the NVMCON register.
A program/erase operation is necessary for programming or erasing the internal Flash program memory in RTSP mode.
The program or erase operation is automatically timed by the device and is nominally 2 m sec in duration. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished.
The CPU stalls (waits) until the programming operation is finished. The CPU will not execute any instruction or respond to interrupts during this time. If any interrupts do occur during the programming cycle, then they will remain pending until the cycle completes.
The user can erase and program Flash Program Memory by rows (32 instruction words). The general process is as follows:
1. Read one row of program Flash (32 instruction words) and store into data RAM as a data “image”. The RAM image must be read from an even 32-word program memory address boundary.
2. Update the RAM data image with the new program memory data.
3. Erase program Flash row.
4. Write 32 instruction words of data from RAM into the Flash program memory write latches.
5. Program 32 instruction words into program Flash.
6. Repeat steps 1 through 6, as needed, to program the desired amount of Flash program memory
The user should remember that the minimum amount of program memory that can be modified using RTSP is 32 instruction word locations. Therefore, it is important that an image of these locations be stored in general purpose RAM before an erase cycle is initiated. An erase cycle must be performed on any previously written locations before any programming is done.
RTSP may be used to write to the Device Configuration registers. RTSP allows each Configuration register to be individually rewritten without first performing an erase cycle.
Caution must be exercised when writing the Configuration registers since they control critical device operating parameters, such as the system clock source, PLL multiplication ratio and WDT enable.
The procedure for programming a Device Configuration register is similar to the procedure for Flash program memory, except that only TBLWTL instructions are required. This is because the upper 8 bits are unused in each Device Configuration register. Furthermore, bit 23 of the table write address must be set to access the Configuration registers.
1. Write the new configuration value to the table write latch using a TBLWTL instruction.
2. Configure NVMCON for a Configuration register write (NVMCON = 0x4008).
3. Disable interrupts, if enabled.
4. Write the key sequence to NVMKEY.
5. Start the write sequence by setting WR (NVMCON<15>).
6. CPU execution will resume when the write is finished.
7. Re-enable interrupts, if needed.
The EEPROM block is accessed using table read and write operations similar to the program memory. The TBLWTH and TBLRDH instructions are not required for EEPROM operations since the memory is only 16-bits wide. The program and erase procedures for the data EEPROM are similar to those used for the Flash program memory, except they are optimized for fast data access. The following programming operations can be performed on the data EEPROM:
The data EEPROM is readable and writable during normal operation (full VDD operating range).
Unlike the Flash program memory, normal program execution is not stopped during an EEPROM program or erases operation.
EEPROM erase and program operations are performed using the NVMCON and NVMKEY registers. The programming software is responsible for waiting for the operation to complete.
The software may detect when the EEPROM erase or programming operation is complete by one of three methods:
Further programming operations can be handled in the ISR.
1. Erase one EEPROM word.
2. Write data word into data EEPROM write latch.
3. Program the data word into the EEPROM.
If multiple words need to be programmed into the EEPROM, it is quicker to erase and program 16 words (1 row) at a time. The process to program 16 words of EEPROM is:
1. Read one row of data EEPROM (16 words) and store into data RAM as a data “image”.
2. Update the data image with the new data.
3. Erase the EEPROM row.
4. Write the 16 data words into the data EEPROM write latches.
5. Program a row into data EEPROM.
The TBLPAG and NVMADR registers must be loaded with the data EEPROM address to be erased. Since one word of the EEPROM is accessed, the LSB of the NVMADR has no effect on the erase operation. The NVMCON register must be configured to erase one word of EEPROM memory.
Setting the WR control bit (NVMCON<15>) initiates the erase. A special unlock or key sequence should be written to the NVMKEY register before setting the WR control bit.
The unlock sequence needs to be executed in the exact order shown without interruption. Therefore, interrupts should be disabled prior to writing the sequence.
Assuming the user has erased the EEPROM location to be programmed, use a table write instruction to write one write latch. The TBLPAG register is loaded with the 8 MSBs of the EEPROM address.
The 16 LSBs of the EEPROM address are automatically captured into the NVMADR register when the table write is executed. The LSB of the NVMADR register has no effect on the programming operation. The NVMCON register is configured to program one word of data EEPROM.
Setting the WR control bit (NVMCON<15>) initiates the programming operation. A special unlock or key sequence should be written to the NVMKEY register before setting the WR control bit. The unlock sequence needs to be executed in the exact order shown without interruption.
Therefore, interrupts should be disabled prior to writing the sequence.
A TBLRD instruction reads a word at the current program word address. This example uses W0 as a pointer to data Flash. The result is placed into register W4.
The program memory map is divided into the user program space and the user configuration space. The user program space contains the Reset vector, interrupt vector tables, program memory and data EEPROM memory. The user configuration space contains non-volatile configuration bits for setting device options and the device ID locations.
A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC30F device clears its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000.
The main program starts at the location 0x000120. The location 0x000000 contains GOTO instruction, and location 0x000002 contains value 0x000120. During each reset of the device, from the location 0x000000 GOTO instruction is read and from the location 0x000002 the address is read where to jump (in this case 0x000120). The program starts execution from the location 0x000120.
After the first two locations is the interrupt vector table serving, for specifying the locations where the interrupt subprograms are. It consists of 62 locations. The next two locations (0x000080 and 0x000082) are reserved for internal purposes. Then, there is the alternative interrupt vector table with another 62 locations. At the address 0x000100 is the start of the space in the program memory for the main program and subprograms. The maximum address of the program space is 0x0007FFE (total of 16K locations). After this address is the program memory configuration space.
Data memory (RAM) serves for storing and keeping data required for the proper operation of the programs. Depending on the program in progress, it can, but does not have to, be split into two sections. For DSP2 instruction set the data memory is considered to consist of two sections. The two data spaces are accessed by using two address generation units and separate data paths, i.e. two data can be read or written simultaneously.
The dsPIC30F data width is 16-bits. All internal registers and data space memory are organized as 16-bits wide. The dsPIC30F features two data spaces.
The data spaces can be accessed separately (for some DSP instructions) or together as one 64-Kbyte linear address range (for MCU instructions). The data spaces are accessed using two Address Generation Units (AGUs) and separate data paths.
Data memory addresses between 0x0000 and 0x07FF are reserved for the device special function registers (SFRs). The SFRs include control and status bits for the CPU and peripherals on the device.
The RAM begins at address 0x0800 and is split into two blocks, X and Y data space. For data writes, the X and Y data spaces are always accessed as a single, linear data space. For data reads, the X and Y memory spaces can be accessed independently or as a single, linear space.
Data reads for MCU class instructions always access the X and Y data spaces as a single combined data space. Dual source operand DSP instructions, such as the MAC instruction, access the X and Y data spaces separately to support simultaneous reads for the two source operands.
MCU instructions can use any W register as an address pointer for a data read or write operation. During data reads, the DSP class of instructions isolates the Y address space from the total data space. W10 and W11 are used as address pointers for reads from the Y data space.
The remaining data space is referred to as X space, but could more accurately be described as “X minus Y” space. W8 and W9 are used as address pointers for data reads from the X data space in DSP class instructions.
The dsPIC30F contains an X AGU and a Y AGU for generating data memory addresses. Both X and Y AGUs can generate any effective address (EA) within a 64-Kbyte range. However, EAs that are outside the physical memory provided will return all zeros for data reads and data writes to those locations will have no effect. Furthermore, an address error trap will be generated. For more information on address error traps, refer to Section 6. “Reset Interrupts”.
The X AGU is used by all instructions and supports all Addressing modes.
The X AGU consists of a read AGU and a write AGU, which operate independently on separate read and write buses during different phases of the instruction cycle. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space. It is also the X address space data path for the dual operand read instructions. The X write data bus is the only write path to the combined X and Y data space for all instructions.
The X RAGU starts its effective address calculation during the prior instruction cycle, using information derived from the just pre-fetched instruction. The X RAGU EA is presented to the address bus at the beginning of the instruction cycle.
The X WAGU starts its effective address calculation at the beginning of the instruction cycle. The EA is presented to the address bus during the write phase of the instruction. Both the X RAGU and the X WAGU support modulo addressing. Bit-reversed addressing is supported by the X WAGU only.
The Y data memory space has one AGU that supports data reads from the Y data memory space. The Y memory bus is never used for data writes. The function of the Y AGU and Y memory bus is to support concurrent data reads for DSP class instructions.
The Y AGU timing is identical to that of the X RAGU, in that it’s effective address calculation starts prior to the instruction cycle, using information derived from the pre-fetched instruction. The EA is presented to the address bus at the beginning of the instruction cycle.
The Y AGU supports Modulo Addressing and Post-modification Addressing modes for the DSP class of instructions that use it.
The Y AGU supports Modulo Addressing and Post-modification Addressing modes for the DSP class of instructions that use it.
The Y AGU does not support data writes. All data writes occur via the X WAGU to the combined X and Y data spaces. The Y AGU is only used during data reads for dual source operand DSP instructions.
The dsPIC30F instruction set provides a broad suite of instructions which supports traditional microcontroller applications and a class of instructions which supports math intensive applications. Since almost all of the functionality of the PIC micro instruction set has been maintained, this hybrid instruction set allows a friendly DSP migration path for users already familiar with the PIC micro microcontroller.
The dsPIC30F instruction set has two classes of instructions: MCU instructions and DSP instructions. These two instruction classes are seamlessly integrated into the architecture and are carried out from a single execution unit.
The instruction set includes many addressing modes and was designed for optimum C compiler efficiency. With just a few exceptions, instructions execute in a single cycle.
The exceptions are instructions that change the program flow (BRA, CALL, etc.), the double-word move (MOV.D) instruction and program memory read/write (table) instructions.
For most instructions, the dsPIC30F is capable of executing a data memory read, a working register data read, a data memory write and a program memory (instruction) read, all during one instruction cycle. As a result, three-operand instructions can be supported, allowing A + B = C type operations to be executed in a single cycle.
The dsPIC instruction set has the following key features, some of which are common to other processors, and some of which are not.
The dsPIC30F instruction set contains 94 instructions, which can be grouped into the ten functional Categories,
Most instructions have several different addressing modes and execution flows, which require different instruction variants. For instance, there are six unique ADD instructions and each instruction variant has its own instruction encoding.
Most instructions execute in a single cycle, with the exception of DO, LNK, MOV.Q, TBLRDH, TBLRDL, TBLWTH, TBLWTL, ULNK and instructions that change the program counter.
These instructions require 2 cycles to execute, with the extra cycle executed as NOP. Skip instructions which skip over a 2-word instruction require 3 instruction cycles to execute, with 2 cycles executed as NOP. The TRAP instruction executes in 4 cycles, which includes exception processing.
Almost all instructions consume one instruction word with the exception of the CALL, DO and GOTO instructions. These instructions require two words of memory because their opcodes embed large literal operands.
Usually the programs for the dsPIC devices are written in some of the higher programming languages. However, sometimes it is required that a section of the code is written in the assembler. This need is particularly emphasized for the processes involving complex processing.
The optimization is possible in some of the higher programming languages, but it is most efficient when using the assembler, assuming that the architecture of the dsPIC30F devices is known. In these cases the core of the algorithm (most demanding part of the program) is programmed using the assembler.
The basic problem when using the assembler instruction set is data memory access, which could be done in several ways. Each of these has its merits and deficiencies. It is thus very important to know the addressing modes and use them correctly while writing a program.
Each assembler instruction can be divided into two parts. The first part of an instruction is the operation which is carried out (like mov, add, etc.) and the second is the operand(s). The operand is a value undergoing the operation. E.g. the instruction DEC W0, W1 carries out the operation of decrementing, defined by DEC, and the operands are the values in the registers W0 and W1.
The dsPIC30F supports three native Addressing modes for accessing data memory, along with several forms of immediate addressing.
Data accesses may be performed using file register direct or register indirect addressing, and immediate addressing allows a fixed value to be used by the instruction.
File register addressing provides the ability to operate on data stored in the lower 8K of data memory (Near RAM), and also move data between the working registers and the entire 64K data space. Register direct addressing is used to access the 16 memory mapped working registers, W0:W15.
Register indirect addressing is used to efficiently operate on data stored in the entire 64K data space, using the contents of the working registers as an effective address.
Immediate addressing does not access data memory, but provides the ability to use a constant value as an instruction operand.
File register addressing is used by instructions which use a predetermined data address as an operand for the instruction. The majority of instructions that support file register addressing provide access to the lower 8 Kbytes of data memory, which is called the Near RAM. However, the MOV instruction provides access to all 64 Kbytes of memory using file register addressing.
This allows one to load data from any location in data memory to any working register, and store the contents of any working register to any location in data memory.
It should be noted that file register addressing supports both byte and word accesses of data memory, with the exception of the MOV instruction, which accesses all 64K of memory as words.
Register direct addressing is used to access the contents of the 16 working registers (W0:W15). The Register Direct Addressing mode is fully orthogonal, which allows any working register to be specified for any instruction which uses register direct addressing, and it supports both byte and word accesses.
Instructions which employ register direct addressing use the contents of the specified working register as data to execute the instruction, so this Addressing mode is useful only when data already resides in the working register core.
Register indirect addressing is used to access any location in data memory by treating the contents of a working register as an effective address (EA) to data memory.
Essentially, the contents of the working register become a pointer to the location in data memory which is to be accessed by the instruction.
This Addressing mode is powerful, because it also allows one to modify the contents of the working register, either before or after the data access is made, by incrementing or decrementing the EA. By modifying the EA in the same cycle that an operation is being performed, register indirect addressing allows for the efficient processing of data that is stored sequentially in memory.
Direct memory addressing is the mode where the operand is at the memory location specified by the instruction.
This means that the operation is accompanied by the address in the memory where the value undergoing the operation is located.
An example of this mode can be when the task is to take the value located in an address in the memory and transfer it to a general purpose register (W0...W15).
MOV 0x0900, W0.
This defines the operation of moving MOV (Move) while the operands are the value at the address 0x0900 in the data memory and the value kept in the register W0.
The flow of operations is the following:
As already mentioned, indirect register addressing allows processing several data, sequentially saved in the memory. This is accomplished by changing automatically the value of the register used for indirect register addressing.
There are four methods of changing the register value in the process of indirect register addressing:
In the pre-increment and pre-decrement addressing modes the value of the register is changed (increased or decreased) first and then the operand address is read.
In the post-increment and post-decrement addressing modes the value of the register is read first and then changed.
In this way the register values are increased or decreased in two steps. The reason that there are two steps is because 16-bit words are in question.
Of course, it is possible to read only one byte, but it should be specified that an 8-bit operation is being executed. Otherwise, 16-bit operation is understood.
This example writes zeros to six sequential locations in memory.
The instruction REPEAT has the consequence that the subsequent operation is executed the specified number of times plus one, i.e. MOV W2, [W1++] will be executed six times.
All operations are 16-bit, unless specified otherwise. This means that one memory location contains two bytes. Even if the operation was 8-bit, the value of the register would be incremented by two, not by one.
Literal addressing is the addressing mode where the operand is located immediately after the operation. It is not required to read any register or memory location. The operand is carried together with the operation code as a constant to be used during the execution of the instruction.
The size of the constant depends on the operation to be executed.
The constant can be signed or unsigned and can be saved with a different number of bits. It is customary to specify the limitations in one of the following ways:
These are the assembler instructions which are very seldom used if the programming is performed in a higher level language, but it is of considerable importance to know the limitations in order to use correctly certain instructions of the higher level languages.
E.g. shift operand (instructions ASR, LSR, SL) can be done within the range 0-16, which is logical since the 16-bit data are involved.
ADD W1, #4, W2
In the example the value of the register W1 is added 4 and the result is written into W2. For the second operand the literal addressing is used. From the table it can be seen that with the instruction ADD one can use constants within the range 0...31.
Individual instructions can use different ranges. E.g. the instruction ADD has three forms for literal addressing. This should be taken care of only while writing a part of the program using the assembler. When using higher programming languages (PASCAL, C, BASIC), the compiler takes care of the form that should be allocated to a given instruction.
The Addressing modes demonstrate the Indirect Addressing mode capability of the dsPIC30F. Due to operation encoding and functional considerations, not every instruction which supports indirect addressing supports all modes. The majority of instructions which use indirect addressing support the No Modify, Pre-Increment, Pre-Decrement, Post-Increment and Post-Decrement Addressing modes. The MOV instructions, and several accumulator based DSP instructions, are also capable of using the Register Offset Addressing mode.
The dsPIC30F provides support for two special Register Indirect Addressing modes, which are commonly used to implement DSP algorithms. Modulo (or circular) addressing provides an automated means to support circular data buffers in X and/or Y memory.
Modulo buffers remove the need for software to perform address boundary checks, which can improve the performance of certain algorithms. Similarly, Bit-Reversed addressing allows one to access the elements of a buffer in a non-linear fashion. This Addressing mode simplifies data re-ordering for radix-2 FFT algorithms and provides a significant reduction in FFT processing time.
In immediate addressing, the instruction encoding contains a predefined constant operand, which is used by the instruction. This Addressing mode may be used independently, but it is more frequently combined with the File Register, Direct and Indirect Addressing modes. The size of the immediate operand which may be used varies with the instruction type. Constants of size 1-bit (#lit1), 4-bit (#bit4, #lit4 and #Slit4), 5-bit (#lit5), 6-bit (#Slit6), 8-bit (#lit8), 10-bit (#lit10 and #Slit10), 14-bit (#lit14) and 16-bit (#lit16) may be used.
Constants may be signed or unsigned and the symbols #Slit4, #Slit6 and #Slit10 designate a signed constant. All other immediate constants are unsigned. Table 4-4 shows the usage of each immediate operand in the instruction set.
The dsPIC30F has a 23-bit Program Counter (PC). The PC addresses the 24-bit wide program memory to fetch instructions for execution, and it may be loaded in several ways.
For byte compatibility with the Read and Write instructions, each instruction word consumes two locations in program memory. This means that during serial execution, the PC is loaded with PC+2.
Several methods may be used to modify the PC in a non-sequential manner, and both absolute and relative changes may be made to the PC.
The change to the PC may be from an immediate value encoded in the instruction, or a dynamic value contained in a working register.
When DO looping is active, the PC is loaded with the address stored in the DOSTART register, after the instruction at the DOEND address is executed.
For exception handling, the PC is loaded with the address of the exception handler, which is stored in the interrupt vector table. When required, the software stack is used to return scope to the foreground process from where the change in program flow occurred.
Since the dsPIC30F data memory is byte addressable, most of the base instructions may operate in either Byte mode or Word mode. When these instructions operate in Byte mode, the following rules apply:
It should be noted that data addresses are always represented as byte addresses. Additionally, the native data format is little-endian, which means that words are stored with the Least Significant Byte at the lower address, and the Most Significant Byte at the adjacent, higher Address.
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