The main objective of project is implement the LatticeMico32, the 32-bit soft core processor from Lattice, to a Xilinx FPGA. In this tutorial we will be using the Spartan 6, XC6SLX9 FPGA Kit.
The LatticeMico32TM is a configurable 32-bit soft processor core for Lattice Field Programmable Gate Array (FPGA) devices. By combining a 32-bit wide instruction set with 32 general-purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. With separate instruction and data buses, this Harvard architecture processor allows for single-cycle instruction execution as the instruction and data memories can be accessed simultaneously. Additionally, the LatticeMico32 uses a Reduced Instruction Set Computer (RISC) architecture, thereby providing a simpler instruction set and faster performance. As a result, the processor core consumes minimal device resources, while maintaining the performance required for a broad application set. Some of the key features of this 32-bit processor include:
The LatticeMico32 processor uses a 32-bit, 6-stage pipeline, as shown in Figure 3 on page 6. It is fully bypassed and interlocked. The bypass logic is responsible for forwarding results back through the pipeline, allowing most instructions to be effectively executed in a single cycle. The interlock is responsible for detecting read-after-write hazards and stalling the pipeline until the hazard has been resolved. This avoids the need to insert nop directives between dependent instructions, keeping code size to a minimum, as well as simplifying assembler-level programming.
The six pipeline stages are:
Finally 32-bit lattice processor successfully implemented in Spartan-6 FPGA Starter kit and output verified with LED C Code.
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