LM32 Processor porting to Spartan-6 FPGA

Porting the LM32 processor to Spartan-6 FPGA

Overall rating

The main objective of project is implement the LatticeMico32, the 32-bit soft core processor from Lattice, to a Xilinx FPGA. In this tutorial we will be using the Spartan 6, XC6SLX9 FPGA Kit.

Tool required

  • Software: Xilinx ISE 14.7i
  • Language: Verilog, C
  • Hardware: 1.Spartan6 FPGA kit

Block Diagram



The LatticeMico32TM is a configurable 32-bit soft processor core for Lattice Field Programmable Gate Array (FPGA) devices. By combining a 32-bit wide instruction set with 32 general-purpose registers, the LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets, including communications, consumer, computer, medical, industrial, and automotive. With separate instruction and data buses, this Harvard architecture processor allows for single-cycle instruction execution as the instruction and data memories can be accessed simultaneously. Additionally, the LatticeMico32 uses a Reduced Instruction Set Computer (RISC) architecture, thereby providing a simpler instruction set and faster performance. As a result, the processor core consumes minimal device resources, while maintaining the performance required for a broad application set. Some of the key features of this 32-bit processor include:

  • ‹ RISC architecture
  • ‹ 32-bit data path
  • 32-bit instructions
  • 32 general-purpose registers
  • Up to 32 external interrupts
  • Optional instruction cache
  • Optional data cache
  • Dual WISHBONE memory interfaces (instruction and data)

Pipeline Architecture

The LatticeMico32 processor uses a 32-bit, 6-stage pipeline, as shown in Figure 3 on page 6. It is fully bypassed and interlocked. The bypass logic is responsible for forwarding results back through the pipeline, allowing most instructions to be effectively executed in a single cycle. The interlock is responsible for detecting read-after-write hazards and stalling the pipeline until the hazard has been resolved. This avoids the need to insert nop directives between dependent instructions, keeping code size to a minimum, as well as simplifying assembler-level programming.

The six pipeline stages are:

  • ‹ Address – The address of the instruction to execute is calculated and sent to the instruction cache.
  • Fetch – The instruction is read from memory.
  • Decode – The instruction is decoded, and operands are either fetched from the register file or bypassed from the pipeline. PC-relative branches are predicted by a static branch predictor.
  • Execute – The operation specified by the instruction is performed. For simple instructions such as addition or a logical operation, execution finishes in this stage, and the result is made available for bypassing.
  • Memory – For more complicated instructions such as loads, stores, multiplies, or shifts, a second execution stage is required.
  • Writeback – Results produced by the instructions are written back to the register file

Source Code


#include "MicoUtils.h"

#include "MicoGPIO.h"

#include "stdio.h"

#include "DDStructs.h"

#include "LookupServices.h"

#include "MicoFileDevices.h"


int main(void){

            unsigned char cnt = 0;

            int i;


            MicoGPIOCtx_t *leds = (MicoGPIOCtx_t *)MicoGetDevice("gpio");



                        MICO_GPIO_WRITE_DATA(leds, 0xAA000000);



                        MICO_GPIO_WRITE_DATA(leds, 0x55000000);








Finally 32-bit lattice processor successfully implemented in Spartan-6 FPGA Starter kit and output verified with LED C Code.

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