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User Manual for 8255 Interface Card

Introduction to 8255 interface card

PS-ADD-ON 8255 interface card is designed to study the features of Intel 8255, PS- 8255 Interface card consist of 12 nos. of point LED’s for displaying device logic output, 8nos of slide switches to give digital input and 4nos of tact switches for interrupt generating interrupt. PS-ADD-ON 8255 is user friendly facilitating the beginners to learn the operation of programmable peripheral interface. Address lines, Chip select lines and the Power lines are terminated with 50-pin connector.

Specification

8255 (programmable peripheral interface )

  • Essential hardware is provided to operate Mode 0, Mode 1 and Mode 2
  • 8 No. SPDT switches is provided at Port A for giving 8 TTL inputs
  • 8 No of LED’s provided at Port B for outputs
  • Port A and Port B lines are terminated to 20 pin header
  • 50 pin FRC connector to interface with 8051/8086/8091 Trainer kits
  • 20 pin FRC is provided for high reliability
  • 4 No. of Tact switches in Port C for generating an interrupt

50-pin Box Header

All data| control lines | Power lines terminated at box connector

50-pin FRC Cable

To connect host boards (Microcontroller/Processor)

Card Features

  • 8 Nos. of Slide Switches and 4 Nos. of push button
  • 12 Nos. of LED
  • 50-pin Box Connector
  • 20-pin Box Connector

Kit Includes

  • 8255 Programmable peripheral interface IC
  • 8 Nos. of Slide Switches and 4 Nos. of push button
  • 12 Nos. of LED
  • 50 pin FRC Interface Cable

Hardware Description of 8255 (UART) Interface

programmable-peripheral-interface-card-blok-diagram

The 8255 has been designed as general purpose programmable I/O device, compatible with Intel Microprocessors. It contains three 8 bit ports which can be configured by software means to provide any one of the three programmable data transfer modes available with 8255. In PS- 8255 Interface card Port A is configured as Input connected to slide switches and Port B configured as output connected to LED and Port C as both Input and output mode. And Port C can be configured as both input and output.

Pin Diagram f 8255 PPI

pin-diagram-of-8255-ppi

Mode Selection of 8255

There are three basic modes of operation than can be selected by the system software:

Mode 0 - Basic Input/output

Mode 1 - Strobe Input/output

Mode 2 - Bidirectional Bus


mode-selection-for-programmable-peripheral-interface-card

Hardware Configuration of 8255 With 8051/8086/8085

 

 

50 PIN HEADER

8255

CONNECTTION

OUTPUT

CONTROL L LINES

A1

A1

Connect 50 pin FRC cable between interface card and trainer kit.

Output for 8255 interface card is based on mode selection and output will be on LED or in memory location

A2

A2

RD

RD

WR

WR

RST

RST

CS9

CS

8255 – DATA LINES

D0

D0

D1

D1

D2

D2

D3

D3

D4

D4

D5

D5

D6

D6

D7

D7

VCC

VCC

VCC

GND

GND

GND



Programs on Ps-Addon 8255(UART) Interface Card

 

a) 8255 Interface with 8051 Trainer Kit

8051 MICRO CONTROLLER ON BOARD I/O DECODING ADDRESS

CONTROL

ADDRESS

Control REG

40A6H

PORT A

40A0H

PORT B

40A2H

PORT C

40A4H



Program 1:

 

Aim:

To initialize Port A as an input port in mode - 0 & to input data set by the SPDT switches through Port A.

ADDRESS

OPCODE

MNEMONICS

9100

90 40A6

MOV DPTR, #40A6

9103

74 90

MOV A, #90

9105

F0

MOVX @DPTR, A

9106

90 40A0

MOV DPTR, #40A0

9109

E0

MOVX A, @DPTR

910A

90 92 00

MOV DPTR, #9200H

910D

F0

MOVX @DPTR, a

910E

80 FE

HLT: SJMP HLT



Procedure:

Enter the program starting from the user Ram address 9100H. Set a known data at the SPDT switches. Execute the program. The above program initializes port A as an input port. The data as set by the SPDT switch settings is input into the accumulator and is stored at the location 9200H. Please verify whether the data at 9200 is the same as that set by SPDT switches.

Program 2:

 

Aim:

To initialize PORT A as input port & PORT B as output port in mode - 0. To Input data at port as set by the SPDT switch & to output the same Data to port b to glow the LEDS accordingly.

ADDRESS

OPCODE

MNEMONICS

9100

90 40 A6

MOV DPTR, #40A6

9103

74 90

MOV A, #90

9105

F0

MOVX @DPTR, A

9106

90 40 A0

MOV DPTR, #40A0

9109

E0

MOVX A, @DPTR

910A

90 40 A2

MOV DPTR, #40A2

910D

F0

MOVX @DPTR, A

910E

80 FE

HLT: SJMP HLT



Procedure:

Enter the program starting form user RAM address 9100H set a known data at the SPDT switches. Execute the program. The data as set by the SPDT switch settings is made output to Port B. Please verify visually that the data output at the LEDs is the same as that set by the SPDT switch settings.

Program 3:

 

Aim:

To initialize PORT C as an output port in mode - 0 & to explain the bit Set & reset feature of PORT C.

ADDRESS

OPCODE

MNEMONICS

9100

90 FF C6

MOV DPTR, #40A6H

9103

74 90

MOV A, #90

9105

F0

MOVX @DPTR, A

9106

90 FF C4

MOV DPTR, #40A4H

9109

74 80

MOV A, #80

910B

F0

MOV @DPTR, A

910C

80 FE

HLT: SJMP HLT



b)8255 Interface with 8085 Trainer Kit

 

CONTROL

ADDRESS

Control REG

66H

PORT A

60H

PORT B

62H

PORT C

64H

 

Program 1:

Aim:

To initialize port A as an Input port in mode-0 and to input the data set by the SPDT switches through port A and store the data at RAM location 9200H.

ADDRESS

OPCODE

MNEMONICS

9100

3E 90

MVI A, 90

9102

D3 66

OUT 066H

9104

DB 60

IN 060H

9106

32 00 92

STA 9200H

9109

76

HLT



Procedure:

Enter the program starting from the user Ram address 9100H. Set a known data at the SPDT switches. Execute the program. The above program initializes port A as an input port. The data as set by the SPDT switch settings is input into the accumulator and is stored at the location 9200H. Please verify whether the data at 9200 is the same as that set by SPDT switches.

Program 2:

 

Aim:

 

ADDRESS

OPCODE

MNEMONICS

9100

3E 90

MVI A, 90

9102

D3 66

OUT 066H

9104

DB 60

IN 060H

9106

D3 C62

OUT 062H

9108

76

HLT



Procedure:

Enter the program starting from the user RAM address 9100H. Set a known data at the SPDT switches. Execute the program. The above program initializes port A as an input port and port B as output port. The data as set by the SPDT switch settings is input to the accumulator and is outputted to port B. Please verify visually that the data output at the LEDs is the same as that set by the SPDT switch settings

Program 3:

 

Aim:

To initialize port C as output port in mode-0 and to output data at port C to glow the LEDs accordingly

ADDRESS

OPCODE

MNEMONICS

9100

3E 90

MVI A, 90

9102

D3 66

OUT 066H

9104

3E 01

MVI A, 01

9106

D3 64

OUT 064H

9108

76

HLT



Procedure:

Enter the program starting from the user RAM address 9100H. Execute the program. In the design used in our board, PC0, PC1, PC3, PC2 bits of Port C are connected to LEDs. So, a data output at any one these lines glows the corresponding LED. In the above program, we output a "one" to the PC0 bit of port C. It can be visually checked by the LED display that the PC0 bit goes 'high' whereas the other bits of port C remain 'low'.

c) 8255 Interface with 8086 Trainer Kit

 

 

ADDRESS

Control REG

FF56H

PORT A

FF50H

PORT B

FF52H

PORT C

FF54H



Program 1:

 

Aim:

To initialize Port A as input port and port B as output port in mode - 0

ADDRESS

OPCODE

MNEMONICS

1100

BA 56 FF

MOV DX,FF56

1103

EE

OUT DX,AL

1105

BA 50 FF

L1: MOV DX,FF50

1106

EC

IN AL,DX

1109

BA 52 FF

MOV DX,FF52

111C

EE

OUT DX,AL

111D

EB FD

JMP L1

 

Procedure:

Enter the program starting form user RAM address 1100H set a known data at the SPDT switches. Execute the program. The data as set by the SPDT switch settings is made output to Port B. Please verify visually that the data output at the LEDs is the same as that set by the SPDT switch settings.

Program 2:

Aim:

To initialize Port A as an input port in mode - 0

ADDRESS

OPCODE

MNEMONICS

1100

BE 00 15

MOV SI, 1500H

1103

B0 90

MOV AL, 90

1105

BA50 FF

MOV DX,FF56

1108

EE

OUT DX,AL

1109

BA 50 FF

MOV DX,FF50

110c

EC

IN AL,DX

110d

88 04

MOV [SI],AL

110F

F4

HLT



Procedure:

Enter the program starting from the user Ram address 1100H. Set a known data at the SPDT switches. Execute the program. The above program initializes port A as an input port. The data as set by the SPDT switch settings is input into the accumulator and is stored at the location 1500H. Please verify whether the data at 1500 is the same as that set by SPDT switches.

Program 3:

Aim:

To initialize port C as output port in mode – 0

ADDRESS

OPCODE

MNEMONICS

1100

B0 90

MOV AL,90

1102

BA 56 FF

MOV DX,FF56

1105

EE

OUT DX,AL

1106

B0 01

MOV AL,01

1108

BA 54 FF

MOV DX,FF54

110B

EE

OUT DX,AL

110C

F4

HLT