How to Interface DC Motor with FPGA/CPLD UDB

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CPLD/FPGA BoardsThe Universal Development board has external DC motor interfacing, indicated as in Figure. 5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program. Reverse the direction of rotation by reversing the polarity of input.

SKU: dcmotor db Category:

Description

DC Motor

A DC Motor is an electric motor that runs on direct current (DC) electricity. DC Motors were used to run machinery, often eliminating the need for a local steam engine or internal combustion engine.

Interfacing DC Motor with FPGA/CPLD UDB

The Universal Development board has external DC Motor interfacing, indicated as in Figure. 5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program. Reverse the direction of rotation by reversing the polarity of input.

 

Pin Assignment with FPGA/CPLD UDB

DC Motor(5V)

PIN NAME

Dc Motor PWM1

DC_PWM1

DC Motor PWM2

DC_PWM2

DC Motor Enable

DC_EN

 

Circuit Diagram to Interface DC Motor with FPGA/CPLD

VHDL Program for DC Motor using FPGA/CPLD

********************************************************************************

Title : Program for DC Motor

**********************************************************************************

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity dc is port ( clk : in std_logic;

rst : in std_logic;

enable : out std_logic;

output1 : out std_logic;

output2 : out std_logic);

end dc;

architecture Behavioral of dc is begin process(rst,clk) variable i : integer := 0;

begin if rst = '1' then

if clk'event and clk = '1' then enable <= '1';

if i <= 1005000 then i := i + 1;

output1 <= '0';

output2 <= '0';

elsif i > 1005000 and i < 1550000 then i := i + 1;

output1 <= '1';

output2 <= '0';

elsif i = 1550000 then i := 0;

end if;

end if;

end if;

end process;

end Behavioral;

Additional information

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