Generating PWM Signals With Variable Duty Cycle

FPGA based Generating PWM Signals With Variable Duty From 0 to 100

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Field Programmable Gate Arrays (FPGA) provide very good hardware design flexibility. This paper specifies the generation of PWM signals for variable duty cycles using VHDL. Pulse Width Modulation found in large number of applications as a voltage controller. It is used in controlling output voltage of inverter in most of the applications.PWM has a fixed frequency and a variable voltage. Voltage value changes from 0V to 5 V. The advantage of this method is that it is used to generate High-frequency variable duty cycle PWM output. The VHDL code is written and synthesized using Xilinx ISE. Results are verified by downloading the code into SPARTAN 6 FPGA.

Tool required

  • Software: Xilinx ISE 14.7i
  • Language: VHDL
  • Hardware: 1.Spartan6 FPGA kit 2.JTAG

Block Diagram



Pulse Width Modulation (PWM) is an integral part of almost all embedded systems. It is widely used as a control technique in most of the power electronic applications like DC/DC, DC/AC, etc. PWM Inverters are one of those power converters which particularly use PWM concept for its operation. Recently PWM inverters have great popularity in industrial applications because of their superior performance. There are basically two PWM techniques –Analog and Digital Techniques. The disadvantages of these analog methods and are that, they are easily affected by noise and they change with respect to voltage and temperature. Digital methods are good for designing variable PWM signals. They are very flexible and less sensitive to environmental noise. Easy to construct and can be implemented in very fast manner. Reprogramming capability of FPGA makes it suitable to develop any design using FPGA. FPGA reduces the design implementation time. FPGA based designs proves less costly and hence they are economically suitable for small designs. The PWM signal is not constant, the main parameter is a duty cycle D that is a part of PWM period.

Pwm Architecture

To produce the input data to generate the PWM using high speed N-bit free running counter, whose output is compared with register output and stores desired input duty cycle with the help of comparator. The comparator output is set equal to 1 when both these values are equal. This comparator output is used to set RS latch. The overflow signal from counter is used to reset RS latch. The output of RS latch gives the desired PWM output. This overflow signal is also used to load new N-bit duty cycle in Register. PWM has a fixed frequency and a variable voltage. This voltage value changes from 0V to 5 V. The basic PWM generates the signals, which gives the output of PWM, requires a comparator that compares between two values. The first value represents the square signal generated by N bit counter and the second value represents the square signal which contains the information about duty cycle. Counter generates the load signal whenever there is an overflow. Once load signal becomes active, the register loads the new duty cycle value. Load signal is used to reset the latch also. Latch output is a PWM signal. This is varying with change in duty cycle value.

Flow chart


Source Code


library ieee;

use ieee.std_logic_1164.all;

entity pwm is


( clk : in std_logic;

pwm_out : buffer std_logic


end entity;


architecture rtl of pwm is


process (clk)

--variable to count the clock pulse

variable count : integer range 0 to 50000;

--variable to change duty cycle of the pulse

variable duty_cycle : integer range 0 to 50000;

--variable to determine whether to increse or decrese the dutycycle

variable flag : integer range 0 to 1;


if (rising_edge(clk)) then

--increasing the count for each clock cycle

count:= count+1;

--setting output to logic 1 when count reach duty cycle value

--output stays at logic 1 @ duty_cycle <= count <=50000

if (count = duty_cycle) then

pwm_out <= '1';

end if;

--setting output to logic 0 when count reach 50000

--output stays at logic 0 @ 50000,0 <= count <= duty_cycle

if (count = 50000) then

pwm_out <= '0';

count:= 0;

--after each complete pulse the duty cycle varies

if(flag = 0) then

duty_cycle:= duty_cycle+50;


duty_cycle:= duty_cycle-50;

end if;

-- flag changes when duty_cycle reaches max and min value

if(duty_cycle = 50000) then

flag:= 1;

elsif(duty_cycle = 0) then

flag:= 0;

end if;

end if;

end if;

end process;

end rtl;



Here we discussed regarding generation of PWM signals with varying duty cycle using VHDL code and tested on FPGA. A FPGA SPARTAN3 board is used as hardware and ISE10.1 XILINX is used as software. The comparator is necessary to compare between the data available in register and counter to generate suitable PWM signals. The generated PWM signals have a fixed frequency depended on the frequency of square wave, and a variable duty cycle that changes from 0% to 100%. But the frequency can be changed on FPGA board based on our requirement, without changing anything in program. These signals can be used to drive a BLDC motor.

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