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 Introduction

In the world of digital design, engineers use Hardware Description Languages to describe complex logic functions. These are included in design suites such as Xilinx's ISE and similar tools. However, if a digital engineer were to code an adder or create a cosine lookup table each time they were doing a project, it would be reinventing the wheel and a waste of their time. Similarly, if the design engineer had to continually re-code commonly used complex digital circuits in large projects; they would end up wasting more time and money. Because of this, a digital design engineer may just use an IP core. An IP (Intellectual Property) core is a block of HDL code that other engineers have already written to perform a specific function. It is a specific piece of code designed to do a specific job. IP cores can be used in a complex design where an engineer wants to save time. As with any engineering tool, IP cores have their advantages and disadvantages. Although they may simplify a given design, the engineer has to design the interfaces to send and receive data from this “black box”. Also, while an IP core may reduce design time, the engineer frequently has to pay for the right to use the core. In this tutorial, you will be given the chance to incorporate a Xilinx IP core into a simple project.

Objective

In his tutorial, the designer will learn how to use Xilinx's CORE Generator System to incorporate an IP core into a VHDL project thus creating a four-bit Adder/Subtracter. Xilinx cores are often beneficial to use as they are written by engineers with knowledge of the inner components of the FPGA. This allows them to be optimized for speed and space.

Process

☞Use the Xilinx CORE Generator System to create an IP core.

☞Connect the IP Core to the VHDL source as a component.

☞Synthesize and program the Xilinx Spartan 6 FPGA project Board [2].

Implementation

☞Start by creating a project. Launch the Xilinx ISE software. Once the Project Navigator window opens, create a new project by clicking on the File drop-down menu, and selecting New Project. Remember the file location of your project. Change the device properties to match those in the previous labs.

☞Finish creating your project, noting the folder it was created in, and proceed to double click on Create New Source in the Processes window. Choose IP (Coregen & Architecture Wizard) in the left menu, and name the file ‘add_sub’. In the next screen open the tree to Math Functions => Adders & Subtracters => Adder Subtracter v11.0 as shown in the image below. Click Next and Finish.

new-source-wizard-window-spartan-6

Fig. 1. New Source Wizard window

☞After a few seconds a new window (LogiCore) should pop up. Select the options to match those in Fig. 2 and click Generate. The window will disappear and will have created an Adder/Subtracter that operates on two four-bit numbers.

first-page-of-the-logicore-window-spartan-6

Fig. 2. First page of the LogiCore Window

Take a minute to click on the Data Sheet… button on the bottom of the screen. The provided data sheets are essential in larger designs to understand many timing issues associated with a specific core as well as explaining all the different design choices.

☞It will take a few moments to generate all of the files. Progress made can be seen by looking at the messages in the Transcript window. When it is finished, add_sub will be shown in the sources window inside the Project Navigator. At this point, the easiest part in the tutorial has been completed. The hardest part, integrating the core into the project and simulating is yet to come.

☞Go to File, click on Open, and browse to “add_sub.vhd”. This will bring up one of the files created by the CORE Generator System. This does not actually do anything. However, there is some information that needs to be copied from the file, so it is nice to have it handy.

☞Now, click on the New icon to create a new VHDL file. Enter the code in the file as you see it below: (comments being optional)

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

 

-- synopsys translate_off

library UNISIM;

library XilinxCoreLib;

-- synopsys translate_on

 

entity adder_subtracter is

          port (

          A: IN std_logic_VECTOR(3 downto 0);

          B: IN std_logic_VECTOR(3 downto 0);

          ADD: IN std_logic;

          Q: OUT std_logic_VECTOR(4 downto 0);

          CLK: IN std_logic);

end adder_subtracter;

 

architecture behavioral of adder_subtracter is

-------------------------------------------------------------------------

--

-- Component Declaration

--

-- The following lines were taken directly from the add_sub.vho file

-- that Coregen creates for you. It is created in such a way that the

-- designer has to simply cut and paste the Component Declaration statements

-- into the source code as I have done here. The add_sub.vho file
-- is created in the project directory and you can get to it with
-- any text editor

--------------------------------------------------------------------------

 

Click on the add_sub.vho file that was opened earlier in the project. Find the text which looks like this:

 

component add_sub

          port (

          A: IN std_logic_VECTOR(3 downto 0);

          B: IN std_logic_VECTOR(3 downto 0);

          ADD: IN std_logic;

          Q: OUT std_logic_VECTOR(4 downto 0);

          CLK: IN std_logic);

end component;

 

-- Synplicity black box declaration

attribute syn_black_box : boolean;

attribute syn_black_box of add_sub: component is true;
 

Highlight and copy it. Return to the original Untitled VHDL source file and paste it in below the previous code. Below that, type a ‘begin’ statement. Again, return to the add_sub.vho file. Find the following text:

your_instance_name : add_sub

                   port map (

                             A => A,

                             B => B,

                             ADD => ADD,

                             Q => Q,

                             CLK => CLK);

Copy it, and paste it into the VHDL source. Change “your_instance_name” to something shorter, such as UUT. Add an ’end behavioral;’ to the end of the VHDL source file. And now, the entire VHDL source file should look like the following:

ADDER/SUBTRACTER CODE

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

 

-- synopsys translate_off

library UNISIM;

library XilinxCoreLib;

-- synopsys translate_on

 

entity adder_subtracter is

          port (

          A: IN std_logic_VECTOR(3 downto 0);

          B: IN std_logic_VECTOR(3 downto 0);

          ADD: IN std_logic;

          Q: OUT std_logic_VECTOR(4 downto 0);

          CLK: IN std_logic);

end adder_subtracter;

 

architecture behavioral of adder_subtracter is

component add_sub

          port (

          A: IN std_logic_VECTOR(3 downto 0);

          B: IN std_logic_VECTOR(3 downto 0);

          ADD: IN std_logic;

          Q: OUT std_logic_VECTOR(4 downto 0);

          CLK: IN std_logic);

end component;

attribute syn_black_box : boolean;

attribute syn_black_box of add_sub: component is true;

begin

UUT : add_sub

                   port map (

                             A => A,

                             B => B,

                             ADD => ADD,

                             Q => Q,

                             CLK => CLK);

end behavioral;

☞Save the file as “adder_subtracter.vhd”. Add it to your project as an existing source. Highlight the file, and double-click Synthesize in the Processes window. If everything was done correctly, it should synthesize without errors. If there are any warnings, ignore them for now, and in the case that there are errors review the code and steps as pointed out below:

☞Create a new project.

☞Start the CORE Generator System

☞Create the desired IP core.

☞Create the top-level VHDL source.

☞Copy and paste in the component declaration in the generated .vho file, and the instance declaration.

☞Save the new source file and incorporate it into your project.

☞Synthesize the source file and check for errors.

☞Create a new source Implementation Constraints File, and assign the pins as follows in order to use Switch and LEDs of Xilinx Spartan 6 FPGA project Board.

Pin assignment for the adder_subtracter project

NET "CLK" LOC = P85;
NET "A[0]" LOC = P51;
NET "A[1]" LOC = P55;
NET "A[2]" LOC = P56;
NET "A[3]" LOC = P57;
NET "B[0]" LOC = P46;
NET "B[1]" LOC = P47;
NET "B[2]" LOC = P48;
NET "B[3]" LOC = P50;
NET "ADD" LOC = P23;
NET "Q[0]" LOC = P64;
NET "Q[1]" LOC = P66;
NET "Q[2]" LOC = P67;
NET "Q[3]" LOC = P74;
NET "Q[4]" LOC = P34;

You can check the pin assignment with Fig. 4 and Fig. 5:

point-led-interface-from-spartan-6

Fig. 4. Physical Connections between FPGA and LEDs

slide-switches-connections-from-spartan-3-fpga-lab-kit

Fig. 4. Physical Connections between FPGA and Switchess

Double click Generate Programming File. Once a green check mark appears, double click over Configure Device (iMPACT) and follow the instructions in the wizard to program the board. Test the logic by moving switches. Remember, you need to put SW17 (pin p23) in the Xilinx Spartan 6 FPGA project Board in the up position if you want it to add the input, otherwise it will subtract. Finally, the 5-bit result of the Adder/Subtracter is associated to the discrete leds.

Conclusion

Think of how long it would have taken to come up with the four bit adder/subtractor VHDL code from scratch. The importance of IP cores is clearly visible.