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XILINX Chipscope Spartan3an FPGA Evaluation Board


Simulation based method is widely used for debugging the FPGA design on Computers. Time required for simulating complex design for all possible test cases becomes prohibitively large and simulation approach fails. For rapid testing, such designs can be loaded on to the target FPGAs and tested by applying test inputs and directly observing their outputs. As the complexity of the design under test increases, so does the impracticality of attaching test equipment probes to these devices under test. The ChipScope Pro tools integrate key logic analyzer and other test and measurement hardware components with the target design inside the FPGA. Computer based software tool communicate with these hardware components and provide a designer robust logic analyzer solution.

In this tutorial we will use simple UP counter design and test it using chipscope

Couter Design:

Create a new project in the Xilinx ISE and paste the following counter code in top module (counter.vhd):


library IEEE;





entity counter is

   Port ( rst : in STD_LOGIC;

           clk : in STD_LOGIC;

           count : out STD_LOGIC_VECTOR (7 downto 0));

end counter;

architecture Behavioral of counter is

signal tcount : std_logic_vector(7 downto 0);




if rst = '1' then


elsif rising_edge(clk) then

tcount<=tcount + '1';

end if;

end process;

count <= tcount;

end Behavioral;


To assign the constraints to the design, create new file named ‘cntr.ucf’ and add it to ISE project. Paste following constrains in ‘counter.ucf’ file. These constraints are applicable for Spartan-3 Development Board


NET "count[0]" LOC = P16;

NET "count[1]" LOC = P15;

NET "count[2]" LOC = P13;

NET "count[3]" LOC = P12;

NET "count[4]" LOC = P11;

NET "count[5]" LOC = P10;

NET "count[6]" LOC = P8;

NET "count[7]" LOC = P7;

NET "clk" LOC = P57;

NET "rst" LOC = P29;


Configuring the logic analyzer core:

In order to test the counter design we have to configure and insert the logic analyzer core in our design. Follow these steps:

1. In the ‘Sources’ view right click on the top module (counter.vhd) and select ‘New Source’.


2. In the ‘New Source Wizard’ window, select ‘Chipscope Definition and Connection File’ and specify the filename as ‘counter_db’. Click ‘Next’ and then click ‘Finish’.


3. Note that ‘counter_debug.cdc’ file has been added to your ‘Sources’ list and is listed below the selected top module (counter).

counter debug

4. Double click on ‘debug.cdc’ to launch the ChipScope Pro Core Inserter application. This application will integrate the logic analyzer core into our counter design. Do not alter any settings on the first screen. Click ‘Next’.


5. To observe any signal, we have to specify the trigger. Logic analyzer core will start capturing the desired signal upon activation of trigger signal. In this example we want to monitor the counter’s counting action as soon as ‘rst’ signal is deactivated. So we will create two trigger ports. One port will be ‘rst’ signal and another port will be counter’s eight least significant bits.

Set ‘Number of trigger ports’ to 2.
In ‘TRIG0’ frame set ‘Trigger Width’ as 1 (since ‘rst’ is one bit signal).
In ‘TRIG1’ frame set ‘Trigger Width’ as 8 (as we want to observe counter’s 8 least significant bits).
Click Next.


6. Now in this window we will specify capture parameters. We want to use our trigger ports as data ports which will be recorded by logic analyzer. We also want to sample data on rising clock edge.

In ‘Sample On’ list select ‘Rising’.
Set Number of samples to be recorded by changing ‘Data Depth’ to 1024 samples. This will record 1024 samples from the trigger event. You can at the most record 16K samples.
Select both check boxes in ‘Trigger Ports Used As Data’ frame.
Click Next.


7. Now we will specify which signal(s) to be used as Clock and Trigger. Click on ‘Modify Connections’.


8. Select the ‘Clock signals’ Pane, then select ‘clk_BUFG’ signal from the left hand side list and then click on ‘Make Connection’. This will add ‘clk’ signal as the clock signal for logic analyzer.


9. Now select ‘Trigger/Data signals’ pane. Select ‘TP0’ and connect ‘rst_IBUF’ signal to CH0 channel.


10. Similarly click on ‘TP1’ pane and add connect counter’s lower eight bits to eight channels. Click ‘OK’ once you finish making connections.


11. Now in the main window click on ‘Return to Project Navigator’. It will ask for saving the project, click ‘Yes’. Now we are ready to compile the entire counter design along with the logic analyzer core.


12. In the ISE, select top level module ‘counter’ and in the ‘Processes’ pane double click on ‘Analyze Design Using ChipScope’. This will start the process to synthesize combined unit consisting of design under test (in this case counter) and the chipscope cores.

Debugging the design using ChipScope Analyzer tool:

Once the synthesis gets over, ISE will launch the Analyzer tool. Make sure that FPGA board is connected to PC.

1. Once the analyzer tool is running, click on ‘Initialize JTAG Chain’ icon located at the top right corner of the window. This will initialize the JTAG chain and identify the devices found in the chain. A dialog box will appear showing the devices discovered. Click ‘OK’.


2. Now select the FPGA device from the JTAG chain, right click and then select ‘Configure’ to specify the configuration bit stream file.


3. Select the bit stream file ‘cntr.bit’ from the bit stream folder. Then click ‘OK’.



4. After clicking ‘OK’, tool will load the bit stream file into FPGA and check the availability of debugging cores. If debugging core is found tool will show ‘INFO: Found 1 Core Unit in the JTAG device Chain.’ Message in status window.

If you see ‘Found 0 Core …’ message instead, then either you have selected wrong bit stream file or something has gone wrong in one of the previous steps and debugging core has not been inserted properly into the design.

If everything is fine then you will see options for Logic Analyzer core inserted in our design. Now double click on the ‘Trigger Setup’ element to launch trigger setup window. And for trigger port 0 (i.e. ‘rst’ signal) specify the trigger Value 0.


This will make logic analyzer to trigger as soon as ‘rst’ become zero and record 1024 samples on successive clock edges. Note that trigger signals are sampled on rising clock edge. Double click on ‘Waveform’ element to see the waveform.

5. Now everything is ready. To apply the settings and ARM the trigger click on button. After that press the ‘Down’ button on the development board to release the ‘rst’ signal. This will trigger the logic analyzer. Once 1024 samples are recorded, this data will be transferred to PC and will be displayed in the waveform window.


NOTE: To see the names of the trigger ports, you can import the ‘debug.cdc’ file in analyzer tool. Click on File>Import and then select ‘counter_debug.cdc’
For more detailed information on various settings and parameters of ChipScope Pro, refer to ‘ChipScope Pro 11.1 Software and Cores User Guide’.