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VLSI Lab Experiments for Spartan3 FPGA Starter Kit

VLSI Lab Experiments

1.VHDL code and implement on FPGA kit

  • Addition
  • Subtraction
  • Multiplication
  • Division

 
2.VHDL code for

  • 8-bit Digital Output -LED Interface
  • 8-bit Digital Inputs (Switch Interface)

3. 4x4 Matrix Keypad Interface

4.VHDL code for

  • Relay Interface
  • Buzzer Interface

5. VHDL code for 7-Segment Display Interface

6. Stepper Motor Interface

7. Traffic Light Controller Interface

8. VHDL code to simulate 4-Bit Binary Counter by software

9. DC motor Control using PWM Generation

10.2x16 character based LCD Interface

11. Design of MUX and DEMUX implement on FPGA kit

12. Design of Encoder / Decoder / Shift Register, implement on FPGA Kit

1. VHDL code and implement on FPGA kit

  • Addition
  • Subtraction
  • Multiplication
  • Division
  • Hardware - FPGASP3 Kit

Description

Arithmetic operators can perform a variety of operations in VHDL such as addition, subtraction, multiplication and division. VHDL arithmetic operators operate on numeric and physical operand data types. The below table shows the VHDL arithmetic operators and data types required for input as A ,B and output as Y.

 


Operator

Description

Input Data Type

Output Data Type

+

Addition

A + B

A numeric

B numeric

Numeric

-

Subtraction

A – B

A numeric

B numeric

Numeric

*

Multiplication

A* B

A integer or real

B integer or real

Integer or Real

*

Multiplication

A* B

A Physical

B integer or real

Physical

*

Multiplication

A* B

A integer or real

B Physical

Physical

/

Division

A / B

A integer or real

B integer or real

Integer or Real

/

Division

A / B

A Physical

B integer or real

Physical

/

Division

A / B

A integer or real

B Physical

Physical


Connection Details

HW : FPGASP3 Kit ( CON - J6 ) - LED| Switch Card
CODE : PSTRYO-FPGASP3\Code\EXA-1\..............


Addition (Program for4-bit addition using arithmetic operator)

Consider the addition of two numbers of a + b, where a and b are 4 bit numbers and the output of addition is taken in y as 8 bit number.


addition-program-for4-bit-addition-using-arithmetic-operator
Flow Chart

addition-flow-char-for-spartan3
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;                 -- Library declaration

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity code is

 

Port (a : in  STD_LOGIC_VECTOR (3 downto 0); -- input/output declaration

      b : in  STD_LOGIC_VECTOR (3 downto 0);

      y : out STD_LOGIC_VECTOR (7 downto 0));

end code;

 

architecture Behavioral of code is

begin

y <= a + b;                    -- This is a assignment statement

end Behavioral;

 


- Program for Half Adder design using logical operator

A half adder ADD 2 input bits A , B and output the results as 2 bits - 1 bit for the Sum and another 1 bit for the Carryout.


Flow Chart

program-for-half-adder-design-using-logical-operator--flow-chart-for-spartan3
Code Listing

 

library IEEE;                     -- Library declaration

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity halfadder is

       Port ( a: in std_logic;

             b: in std_logic;     -- input / output declaration

            Sum: out std_logic;

       carryout: out std_logic);

       end halfadder;

 

       architecture behavior of halfadder is

       begin

           Sum <= a xor b;        -- This is a signal assignment statement.

           Carryout <= a and b;   -- This is a signal assignment statement.

       end HA_DtFl;

 


Subtraction (Program for 4-bit subtraction using arithmetic operator)

Consider the subtraction of two numbers of a - b, where a and b are 4 bit numbers and the output of subtraction is taken in y as 4 bit number.


subtraction-program-for-4-bit-subtraction-using-arithmetic-operator
Flow Chart

subtraction-flow-chart-for-spartan3
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;           -- Library declaration

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity code is

   Port ( a : in  STD_LOGIC_VECTOR (3 downto 0); -- input / output declaration

          b : in  STD_LOGIC_VECTOR (3 downto 0);

          y : out STD_LOGIC_VECTOR (3 downto 0));

end code;

 

architecture Behavioral of code is

begin

y <= a - b;                       -- This is a assignment statement.

end Behavioral;

 


Multiplication (Program for simple 2x2 multiplications using arithmetic operator)

Consider the multiplication of two numbers as 2 x2 a * b, where a and b are 4 bit numbers and the output of multiplication is taken in y as 8 bit number.


Flow Chart

multiplication-flow-chart-for-spartan3
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;           -- Library declaration

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity code is

  Port ( a : in  STD_LOGIC_VECTOR (3 downto 0);      -- input / output declaration

         b : in  STD_LOGIC_VECTOR (3 downto 0);

         y : out  STD_LOGIC_VECTOR (7 downto 0));

end code;

 

architecture Behavioral of code is

begin

y <= a *  b;                      -- This is a assignment statement

end Behavioral;

 


Multiplication (Program for 2 x 2 combinational array multiplications)

Consider the multiplication of two numbers as 2 x2 a * b, where a and b are 2 bit numbers and the output of multiplication is taken in P as 4 bit number.


multiplication-program-for-2-x-2-combinational-array-multiplications
Flow Chart

multiplication-program-for-2-x-2-combinational-array-multiplications-flow-chart-spartan3
Code Listing

 

library IEEE;                               -- Library declaration

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity mult_arry is

Port (a, b: in std_logic_vector (1 downto 0); -- input / output declaration

 P: out std_logic_vector (3 downto 0));

end mult_arry;

 

architecture MULT_DF of mult_arry is

begin                           

             -- For simplicity propagation delay times

           -- are not considered in this example.

P (0) <= a(0) and b(0);

P (1) <= (a(0) and b(1)) xor (a(1) and b(0));

P (2) <= (a(1) and b(1)) xor ((a(0) and b(1)) and (a(1) and b (0)));

P (3) <= (a(1) and b(1)) and ((a(0) and b(1)) and (a(1) and b (0)));

end MULT_DF;

 


Division (Program to divide even numbers)

Consider the division of two numbers as a / b, where ‘a’ is 8 bit numbers and the output of division is taken in Y as 8-bit number.


Flow Chart

division-flow-char-for-spartan3
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity code is

port ( a : in std_logic_vector(7 downto 0);     --dividend

            b : out std_logic_vector (7 downto 0));

end code;

 

architecture Behavioral of code is

 

begin

b <= CONV_STD_LOGIC_VECTOR((CONV_INTEGER(a)/4),8);

end Behavioral;

 


2. LED & Switch Interface Card

Experiments Covered

  • 8-bit Digital Output -LED Interface
  • 8-bit Digital Inputs (Switch Interface)

Hardware Description

  • LED & Switch Card has 8 nos. of Point LEDs, are the most commonly used components, usually for displaying Logical output of Device pin’s states.
  • LED & Switch Card has 8 Nos. of Slide Switch, to give a digital input to the devices to evaluate the pin states. LED Lines/Switch lines connected by 20pin box connector.

 

20PIN CONNECTOR

MODULES

LED & Switch Card Pin Details

SLIDE SWITCH

1

SW1

 

led--switch-card-pin-details

2

SW2

3

SW3

4

SW4

5

SW5

6

SW6

7

SW7

8

SW8

LED

9

LED1

 

led-selection--spartan-3

10

LED2

11

LED2

12

LED2

13

LED2

14

LED2

15

LED2

16

LED2

PWR

17,19

Vcc

Supply form FPGASP3 Kit

18,20

Gnd


 
8-Bit Digital Output (Program to Blink 8 LEDs at Once)

Description

In this program to blink 8 Nos. of point LEDs at once in 250msec delay, Spartan3 FPGA Starter Kit lines (P77 - P80 and P82 – P85) are configured has LED Outputs. User could verify the result by using “LED & Switch Card” connected to the FPGASP3 Kit at connector J6


Flow Chart

8-bit-digital-output--led-interface-flow-cahr-spartan3
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity code is

port ( clk : in std_logic;                           -- clock i/p

       led : out std_logic_vector(7 downto 0));      -- 8-led o/p

end code;

 

architecture Behavioral of code is

 

begin

process(clk)

variable i,j : integer := 0;

begin

      if clk'event and clk = '1' then

 if i < 25000000 then                    --on delay logic

    i := i + 1;

    led(j) <= '1';

 elsif i = 25000000 then

    i := 0;

    led(7 downto 0) <= "00000000";

 if j < 7 then                           --checking for 8 display

    j := j + 1;

 elsif j = 7 then

    j := 0;

      end if;

     end if;

    end if;

end process;

end Behavioral;

 


8-Bit Digital Input (Program to Read Switch Status and displayed in LEDs)

Description

In this program to give digital inputs from slide switches and switch status could be viewed by point LEDs, In Spartan3 FPGA Starter Kit lines (P60, P63, P68, P69, P70, P73, P74, P76) are configured has Digital Inputs and LEDs configured as (P77-P80 and P82-P85) outputs. User could verify the result by using “LED & Switch Card” connected to the FPGA SPARTAN3 KIT at connector J6


Flow Chart

8-bit-digital-input--slide-switches-interface-flow-char-spartan3
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

 

entity code is

port ( SW : in std_logic_vector(7 downto 0);    ---data i/p

       LED : out std_logic_vector(7 downto 0));  ---data o/p

end code;

 

architecture Behavioral of code is

begin

LED <= SW;                               ---data assignment

end Behavioral;

 


3.4x4 Matrix Keypad Card

Experiments Covered

  • Key Press Displayed in LED
  • Key Press Displayed in LCD

Hardware Description

  • Key arranged by matrix format, FOR each row and column section pulled by high, all row lines (R1 – R4) and column lines (C1 – C4) connected directly by the 20pin box connector.

 

20PIN CONNECTOR

MODULES

4X4 Matrix Keypad Card

SWITCH

1

R1

4x4-matrix-keypad-card 

2

R2

3

R3

4

R4

5

C1

6

C2

7

C3

8

C4

 

9-16

NC

Pins 9-16 Not used

PWR

17,19

Vcc

Supply form FPGASP3 Kit


 

4 X 4 Matrix Keypad Card Interface (program to Scan Row & Column lines in 4 X 4 Matrix Keypad)

Description

In this example to scan Row and Column lines in 4 X 4 Matrix Keypad and view the result in LED. In Spartan3 FPGA lines (P60, P63, P68 and 69) are configured for Horizontal (ROW) lines. Pins (P70, 73, 74 and P76) are configured for Vertical (column) lines. User could verify the result by “4 X 4 Matrix Keypad Interface Card” connected to the FPGA SPARTAN3 KIT at connector J6.


Flow Chart

5x1-matrix-keypad-interface-flow-char-spartan3
Truth Table

4 x4 Matrix

Keypad

Row LEDs lines

Column LEDs lines

D4

D5

D6

D7

D8

D9

D10

D11

SW1

1

0

0

0

1

0

0

0

SW2

1

0

0

0

0

1

0

0

SW3

1

0

0

0

0

0

1

0

SW4

1

0

0

0

0

0

0

1

SW5

0

1

0

0

1

0

0

0

SW6

0

1

0

0

0

1

0

0

SW7

0

1

0

0

0

0

1

0

SW8

0

1

0

0

0

0

0

1

SW9

0

0

1

0

1

0

0

0

SW10

0

0

1

0

0

1

0

0

SW11

0

0

1

0

0

0

1

0

SW12

0

0

1

0

0

0

0

1

SW13

0

0

0

1

1

0

0

0

SW14

0

0

0

1

0

1

0

0

SW15

0

0

0

1

0

0

1

0

SW16

0

0

0

1

0

0

0

1

 

4 X 4 Matrix Keypad Card Interface (Press 4 X 4 Matrix Keypad view result in 2 X16 LCD)

Description

In Spartan3 FPGA lines (P60, P63 and P68) - LCD control lines Pins (P77 to P80 and P82 to P85) LCD data lines. (P32, P33 P35 and P36) - Horizontal (ROW) lines. Pins (P40, P41, P44 and P46) - Vertical (column) lines. User could verify the result by “4X4 Matrix Keypad Interface Card” connected to the FPGA SPARTAN3 KIT at connector J7 and “2X16 LCD Interface Card” connected to the at connector J6.


Flow Chart

matrix-keypad-interface-flow-
4. Relay & Buzzer Interface Card

Experiments Covered

  • Relay Interface
  • Buzzer Interface

Hardware Description

Relay & Buzzer Card , consists of 6 Nos. 5V SPDT Relay with output terminations, and 2 Nos. of continuous buzzer connected to the 20pin box connector to study relay and buzzer modules.


ULN2803 is used as a driver for port I/O lines, drivers output connected to relay modules and buzzers. Connector provided for external power supply if needed.


Relay / Buzzer Module : Make port pins high devices “relay/buzzer” activated.


 

20PIN CONNECTOR

MODULES

Relay & Buzzer Card

RELAYS

1

RELAY1

relay--buzzer-card-tyro 

2

RELAY2

3

RELAY3

4

RELAY4

5

RELAY5

6

RELAY6

BUZZER

7

BUZZER1

8

BUZZER2

 

9-16

NC

Pins 9-16 Not used

PWR

17,19

Vcc

Supply form FPGASP3 Kit

18,20

Gnd

 

Note: Separate switch provided to enable Buzzer ON/Off.


Relay (Toggle Relay On/Off with 1sec Delay)

Description

In this program to toggle relays On/Off continuously with 1 sec delay time. In Spartan3 lines (P60, P63, P68, P69, P70, and P73) are configured for relays. User could verify the result by using “Relay & Buzzer Card” connected to the FPGA SPARTAN3 KIT at connector J6.


Flow Chart

relay-toggle-relay-on-off-
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;          --library declaration

 

entity first is

port ( clk : in std_logic;

       relay : out std_logic_vector(5 downto 0) := "000000");

end first;

 

architecture Behavioral of first is

begin

process(clk)

variable i,j : integer := 0;

begin

if clk'event and clk = '1' then

if i < 50000000 then

i := i + 1;

elsif i = 50000000 then

i := 0 ;

if j < 5 then

j := j + 1;

elsif j = 5 then

j := 0;

end if;

end if;

if j = 0 then

relay <= "100000";

elsif j = 1 then

relay <= "010000";

elsif j = 2 then

relay <= "001000";

elsif j = 3 then

relay <= "000100";

elsif j = 4 then

relay <= "000010";

elsif j = 5 then

relay <= "000001";

end if;

end if;

end process;

end Behavioral;

 


Buzzer (To Generate Sound Continuously On/Off with 1sec Delay)

Description

In this program to generate sound signal continuously with delay of 1sec interval using piezo-electric buzzer. In Spartan3 FPGA lines Buzzer1 (P74) and Buzzer2 (P76) are configured for Buzzers. User could verify the result by using “Relay & Buzzer Card” connected to the FPGA SPARTN3 KIT at connector J6.


Note: In Interfacing card separate switch provided to enable Buzzer On/Off.


Flow Chart

  buzzer-flow-chart
Code Listing

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;                 --library declaration

 

entity first is

port ( clock       : in std_logic;

       buzzer1     : out std_logic;           --i/o declaration

       buzzer2     : out std_logic);

end first;

 

architecture Behavioral of first is

begin

process(clock)

variable i : integer := 0;

begin

if clock'event and clock = '1' then             --delay statement

  if i <= 50000000 then

    i := i + 1;

    buzzer1 <= '1';                      --buzzer1 ON

    buzzer2 <= '0';

  elsif i > 50000000 and i < 100000000 then

    i := i + 1;

    buzzer1 <= '0';

    buzzer2 <= '1';                      --buzzer2 ON

  elsif i = 100000000 then

    i := 0; 

  end if;

 end if;

end process;

end Behavioral;

 


5. 7-segment Display Card

Experiments Covered

  • Simple Message Display("012345")
  • Simple Counter Program(0 - 1000)

Hardware Description

It has 6 nos. of common anode seven segment displays are used. The segment lines of seven segments LED is being terminated at 20pin connector pin 9-to 16. The digit select lines are connected to the 20pin box connector pin1- to pin6. All the common anode displays consume very small amount of current.


 

20PIN CONNECTOR

MODULES

7-Segment Display Card

Digit select lines

1

Digit - 1

7-segment-display-spartan-3 

2

Digit – 2

3

Digit – 3

4

Digit - 4

5

Digit – 5

6

Digit – 6

7

NC

8

NC

Segment Lines

9

Seg - a

10

Seg – b

11

Seg – c

12

Seg – d

13

Seg – e

14

Seg – f

15

Seg – g

16

Seg – dp

PWR

17,19

Vcc

Supply form FPGASP3 Kit

18,20

Gnd


 

7-segment Display (To Display Message “000000” to “ FFFFFF”)

Description

In this program to display simple message “000000” to”FFFFFF” the 7-seg display module. In Spartan3 FPGA lines (P60, P63, P68, P69, P70, and P73) are configured for digit selection lines. Pins (P77 - P80 and P82 – P85) are configured by data lines. User could verify the result by “7-SEG Display Card” connected to the SPARTAN3 KIT at connector J6.


Flow Chart

7-segment-display-flow-chart
7-segment Display (Simple Counter “0-1000”)

Description

In This example to display simple counter for “0- 1000” to the 7-seg display module. In Spartan3 FPGA lines (P60, P63, P68, P69) are configured for (Digit-1 to Digit-4) selection lines. Pins (P77 - P80 and P82 – P85) are configured by data lines. User could verify the result by “7-SEG Display Card” connected to the SPARTAN3 KIT at connector J6.


Flow Chart

7-segment-display--simple--flow-chart