You have no items in your shopping cart.

Subtotal: 0.00

 VLSI Lab Experiments

1. VHDL code and implement on FPGA kit

☞Addition

☞Subtraction

☞Multiplication

☞Division

2. VHDL code for

☞8-bit Digital Output -LED Interface

☞8-bit Digital Inputs (Switch Interface)

3. 5 × 1 Matrix Keypad Interface

4. VHDL code for Buzzer Interface

5. 12 Bit SPI ADC

6. 12 Bit SPI DAC

7. VHDL code to simulate 4-Bit Binary Counter by software

8. 2x16 character based LCD Interface

9. Design of MUX and DEMUX implement on FPGA kit

10. Design of Encoder / Decoder / Shift Register, implement on FPGA Kit



1. VHDL code and implement on FPGA kit

Simple VHDL Program for

☞Addition

☞Subtraction

☞Multiplication

☞Division

Description

Arithmetic operators can perform a variety of operations in VHDL such as addition, subtraction, multiplication and division. VHDL arithmetic operators operate on numeric and physical operand data types. The below table shows the VHDL arithmetic operators and data types required for input as A ,B and output as Y.

 
 

Operator

Description

Input Data Type

Output Data Type

+

Addition

A + B

A numeric

B numeric

Numeric

-

Subtraction

A – B

A numeric

B numeric

Numeric

*

Multiplication

A* B

A integer or real

B integer or real

Integer or Real

*

Multiplication

A* B

A Physical

B integer or real

Physical

*

Multiplication

A* B

A integer or real

B Physical

Physical

/

Division

A / B

A integer or real

B integer or real

Integer or Real

/

Division

A / B

A Physical

B integer or real

Physical

/

Division

A / B

A integer or real

B Physical

Physical

 
 

Addition (Program for4-bit addition using arithmetic operator)

Description :

Consider the addition of two numbers of a + b, where a and b are 4 bit number and the output of addition is taken in y as 8 bit number.



addition-program-for4-bit-addition-using-arithmetic-operator


Code Path :

PSPRIMER-FPGASP3\CODE\Ex-1a1\

Flow Chart



addition-flow-char-for-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; -- Library declaration

use IEEE.STD_LOGIC_ARITH.ALL;

 entity code is

 Port (a : in STD_LOGIC_VECTOR (3 downto 0); -- input/output declaration

b : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (7 downto 0));

end code;

 architecture Behavioral of code is

begin

y <= a + b;  -- This is a assignment statement

end Behavioral;

Program for Half Adder design using logical operator

Description :

A half adder ADD 2 input bits A , B and output the results as 2 bits - 1 bit for the Sum and another 1 bit for the Carryout.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-1a2\

Flow Chart



program-for-half-adder-design-using-logical-operator--flow-chart-for-spartan-3an

Code Listing

library IEEE -- Library declaration

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity halfadder is

Port ( a: in std_logic;
 
b: in std_logic; -- input / output declaration

Sum: out std_logic; 

carryout: out std_logic); 

end halfadder;

architecture behavior of halfadder is

begin

Sum <= a xor b;  -- This is a signal assignment statement.

Carryout <= a and b; -- This is a signal assignment statement.

end HA_DtFl;

Subtraction (Program for 4-bit subtraction using arithmetic operator)

Description :

Consider the subtraction of two numbers of a - b, where a and b are 4 bit numbers and the output of subtraction is taken in y as 4 bit number.



subtraction-program-for-4-bit-subtraction-using-arithmetic-operator

Code Path :

Consider the subtraction of two numbers of a - b, where a and b are 4 bit numbers and the output of subtraction is taken in y as 4 bit number.

Flow Chart



subtraction-flow-chart-for-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; -- Library declaration

use IEEE.STD_LOGIC_ARITH.ALL;

entity code is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0); -- input / output declaration

b : in STD_LOGIC_VECTOR (3 downto 0);

y : out STD_LOGIC_VECTOR (3 downto 0));

end code;

architecture Behavioral of code is

begin

y <= a - b; -- This is a assignment statement.

end Behavioral;

Multiplication (Simple 2x2 multiplications using arithmetic operator)

Description :

Consider the multiplication of two numbers as 2 x2 a * b, where a and b are 4 bit numbers and the output of multiplication is taken in y as 8 bit number.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-1c1\

Flow Chart



multiplication-flow-chart-for-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; -- Library declaration

use IEEE.STD_LOGIC_ARITH.ALL;

entity code is

 Port ( a : in STD_LOGIC_VECTOR (3 downto 0);  -- input / output declaration

   b : in STD_LOGIC_VECTOR (3 downto 0);

   y : out STD_LOGIC_VECTOR (7 downto 0));

end code;

architecture Behavioral of code is

begin
                                                                                                                                                                                                                                                                                              
y <= a * b;    -- This is a assignment statement

end Behavioral;

Multiplication (Program for 2 x 2 combinational array multiplications)

Description :

Consider the multiplication of two numbers as 2 x2 a * b, where a and b are 2 bit numbers and the output of multiplication-program-for-2-x-2-combinational-array-multiplicationsmultiplication is taken in P as 4 bit number.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-1c2\



multiplication-program-for-2-x-2-combinational-array-multiplications

Flow Chart



multiplication-program-for-2-x-2-combinational-array-multiplications-flow-chart-spartan-3an

Code Listing

library IEEE;   -- Library declaration

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity mult_arry is

Port (a, b: in std_logic_vector (1 downto 0); -- input / output declaration

 P: out std_logic_vector (3 downto 0));

end mult_arry;

architecture MULT_DF of mult_arry is

begin;

-- For simplicity propagation delay times

-- are not considered in this example.

P (0) <= a(0) and b(0);

P (1) <= (a(0) and b(1)) xor (a(1) and b(0));

P (2) <= (a(1) and b(1)) xor ((a(0) and b(1)) and (a(1) and b (0)));

P (3) <= (a(1) and b(1)) and ((a(0) and b(1)) and (a(1) and b (0)));

end MULT_DF;

Division (Program to divide even numbers)

Description :

Consider the division of two numbers as a / b, where ‘a’ is 8 bit numbers and the output of division is taken in Y as 8-bit number.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-1d\

Flow Chart



division-flow-char-for-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity code is

port ( a : in std_logic_vector(7 downto 0); --dividend

  b : out std_logic_vector (7 downto 0));

end code;

architecture Behavioral of code is

begin

b <= CONV_STD_LOGIC_VECTOR((CONV_INTEGER(a)/4),8);

end Behavioral;

2. VHDL code for

8-bit Digital Output -LED Interface

Description :

Program to blink 8 Nos. of point LEDs at once in 250ms delay.

Connections :

FPGA Pins (P7,P8,P10,P11,P12,P13,P15 & P16)

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-2a\

Flow Chart



8-bit-digital-output--led-interface-flow-cahr-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity code is

port ( clk : in std_logic;  -- clock i/p

 led : out std_logic_vector(7 downto 0));    -- 8-led o/p

end code;

architecture Behavioral of code is
begin

process(clk)

variable i,j : integer := 0;

begin
if clk'event and clk = '1' then if i < 

25000000 then;
 
--on delay logic; 

i := i + 1;  

led(j) <= '1'; 

elsif i = 25000000 then ; 

i := 0; 

led(7 downto 0) <= "00000000";

 if j < 

7 then; 
--checking for 8 display;
 j := j + 1; 
elsif j = 7 then ; 
j := 0; end if; 
end if; 

 end if;

end process;

end Behavioral;

8-bit Digital Input – Slide Switches Interface

Description :

Program to read switch status and displayed in point LEDs.

Connections :

FPGA Pins (P18,P19,P20,P21,P24,P25,P27 & P28)

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-2b\

Flow Chart



8-bit-digital-input--slide-switches-interface-flow-char-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

entity code is

port ( SW : in std_logic_vector(7 downto 0);   ---data i/p

 LED : out std_logic_vector(7 downto 0)); ---data o/p

end code;

architecture Behavioral of code is

begin

LED <= SW; ---data assignment

end Behavioral;

3. 5x1 Matrix Keypad Interface

Description :

Program to display pressed key(assign) value (Row & Column) status in Point LEDs’

KEYPAD: P29,P30,P31,P32 & P33
Point LEDs: P18,P19,P20,P21 & P24

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-3a\

Flow Chart



5x1-matrix-keypad-interface-flow-char-spartan-3an

5x1 Matrix Keypad Interface

Description :

Program to display pressed key(assign) value (Row, Column) in LCD Module

Connections :

KEYPAD : P29,P30,P31,P32 & P33
LCD Control : P105, P104, P103
LCD Data : P102, P101, P99, P98, P96, P93, P92 & P91

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-3b\

Flow Chart



5x1-matrix-keypad-interface-flow-spartan-3an-

4. VHDL code for Buzzer Interface

Buzzer Interface

Description :

Program to generate sound signal continuously with 1sec delay

Connections :

P64 (Buzzer)

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-4b\

Note : To enable buzzer place jumper J5 at ‘E’ label mark position

Flow Chart



buzzer-interface-flow-char-spartan-3an

Code Listing

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL; --library declaration

entity first is

port ( clock : in std_logic;

 buzzer1 : out std_logic; --i/o declaration

end first;

architecture Behavioral of first is

begin

process(clock)

variable i : integer := 0;

begin

if clock'event and clock = '1' then --delay statement

if i <= 50000000 then

i := i + 1;

buzzer1 <= '1';--buzzer1 ON

elsif i > 50000000 and i < 100000000 then

i := i + 1;

buzzer1 <= '0';

elsif i = 100000000 then

   i := 0;

 end if;

 end if;

end process;

end Behavioral;

5. 12 Bit SPI ADC

ADC Interface

Description :

Program to Perform Analog to Digital Output Conversion.

Connections :

P110 (CS), p111 (SCK), p113 (DIN), p114 (DOUT).

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-4b\

Flow Chart



adc-interface-flow-char-spartan-3an

6. 12 Bit SPI DAC

DAC Interface

Description :

Program to Perform Digital to Analog Output Conversion.

Connections :

P58 (CS), p59 (SCK), p60 (SDI)

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-4b\

Flow Chart



dac-interface-flow-char-spartan-3an

7. VHDL code to simulate 4-Bit Binary Counter by software

COUNTERS

Description :

A counter is a device which stores the number of times a particular event or process has occurred, often in relationship to a clock signal. There are types of counters:

☞up counters | down counters | up/down counters

Examples :

a. 4-bit Up Counter using behavior description
b. 4-bit Down Counter using behavior description
c. 4-bit Up/Down Counter using behavior description

4-bit Up Counter using behavior description

Description :

In this program an up counter has a 1- bit input and a 4- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-8a\

Flow Chart



4-bit-up-counter-using-behavior-description-flow-char-spartan-3an

Code Listing

library IEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is 

 port(Clock, CLR : in std_logic;

 Q : out std_logic_vector(3 downto 0));

 end counter;

 architecture archi of counter is 

 signal tmp: std_logic_vector(3 downto 0);

 begin

 process (Clock, CLR)

 begin

 if (CLR='1') then

tmp <= "0000"; 

 elsif (Clock'event and Clock='1') then

tmp <= tmp + 1;

 end if; 

 end process;

 Q <= tmp;

 end archi;

4-bit Down Counter using behavior description

Description :

In this program a down counter has a 1- bit input and a 4- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-8b\

Flow Chart



4-bit-down-counter-using-behavior-description-flow-char-spartan-3an

Code Listing

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity counter is

 port(Clock, CLR : in std_logic;

 Q : out std_logic_vector(3 downto 0));

 end counter;

 architecture archi of counter is

 signal tmp: std_logic_vector(3 downto 0);

 begin

 process (Clock, CLR)

 begin

 if (CLR='1') then

tmp <= "1111";

 elsif (Clock'event and Clock='1') then 

tmp <= tmp - 1;

 end if; 

 end process; 

 

 Q <= tmp;
end archi;

C) 4-bit Up/Down Counter using behavior description

Description :

The Up/Down control input line simply enables either the upper string or lower string of AND gates to pass the Q/Q' outputs to the succeeding stages of flip-flops. If the Up/Down control line is "high," the top AND gates become enabled. If the Up/Down control line is made "low," the bottom AND gates become enabled.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-8c\

Flow Chart



4-bit-up-down-flow-char-spartan-3an

Code Listing

library ieee;

 use ieee.std_logic_1164.all;

 use ieee.std_logic_unsigned.all;

entity counter is 

port(C, CLR, up_down : in std_logic;

 Q : out std_logic_vector(3 downto 0));

end counter;

architecture archi of counter is 

 signal tmp: std_logic_vector(3 downto 0);

 begin 

 process (C, CLR)

 begin 

 if (CLR='1') then

 tmp <= "0000"; 

 elsif (C'event and C='1') then 

 if (up_down='1') then 

 tmp <= tmp + 1; 

 else 

 tmp <= tmp - 1;

 end if;

 end if;

 end process;

 Q <= tmp;

 end archi;

8. 2x16 character based LCD Interface

2x16 Character LCD Interface

Description :

Program to Display Message “PSPRIMER DEMO” in LCD’s first Line

Connections :

LCD Control : P105 (RS), P104 (RW), P103 (E) LCD Data : P102, P101, P99, P98, P96, P93, P92 & P91

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-9\

Flow Chart



2x16-character-lcd-interface-flowchart-spartan-3an

9. Design of MUX and DEMUX implement on FPGA kit

Multiplexer and De-multiplexer

Multiplexer: MUX

Description :

Multiplexer is a logic circuit that receives binary information from several Inputs and transmits information to single output. The input selected is Controlled by a set of select inputs.

De-multiplexer – Demux

Description :

A de-multiplexer performs the reverse operation of a multiplexer. It is a digital function that receives information on a single line and transmits this information to one of the 2n possible output lines. The output line being selected is determined by the bit combination of the selected lines.

Examples :

8 x 1 Multiplexer design using behavioral description.
1 x 8 de-multiplexer design using gate level description.

8 x 1 multiplexers using behavioral descriptions

Description :

In this program a 8 x 1 multiplexer has eight 1- bit inputs, three 1-bit select line and a 1- bit output. Additional control signals may be added such as enable. The output of the multiplexers depends on the level of the select line.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-11a\



8-x-1-multiplexers-using-behavioral

Facts:

☞The behavioral description describes the system by showing how the outputs behave according to changes in the inputs.

☞In this description we don’t need to know the logic diagram of the system what must be known is how the output behaves in response to change in the input.

☞In VHDL the major behavioral description statement is process.

1 x 8 de-multiplexers using behavioral descriptions

Description :

In this program a 1 x 8 de-multiplexer have one 1- bit inputs, three 1-bit select line and eight 1- bit output. Additional control signals may be added such as enable. The output of the de-multiplexers depends on the level of the select line.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-11b\

Flow Chart



1-x-8-de-multiplexers-using-behavioral-flow-chart-spartan-3an

10. Design of Encoder / Decoder / Shift Register, implement on FPGA Kit

Encoder, Decoder and Shift register

Encoder:

Description :

An encoder has 2n input lines .the output lines generate binary code corresponding to the input value.for example a single bit 4 to 2 encoder takes in 4 bits and output 2 bits.it is assumed. That they are only four types of input signals these are 0001, 0010, 0100 & 1000.

Decoder:

Description :

A decoder is a device which does the reverse of an encoder undoing so that the original information can be retrieved. The same method used to encoder is usually just reversed in order to decode. In digital electronics this would mean that a decoder is a multiple input , multiple output logic circuit that converts coded inputs into coded outputs where the inputs and output s are different. Eg. n to2n.

Shift register:

Description :

Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a bit of data for each register. The data string is presented at 'Data In', and is shifted right one stage each time 'Data Advance' is brought high. At each advance, the bit on the far left (i.e. 'Data In') is shifted into the output. The bit on the far right (i.e. 'Data Out') is shifted out and lost.

Examples :

4 X 2 Encoder design using behavioral description.
2 X 4 Decoder design using conditional statement.
8 bit serial shift register design using behavioral description.

4 X 2 Encoder using behavioral description

Description :

In this program a 4 x 2 encoder has four 1- bit inputs and two 1- bit output. Additional control signals may be added such as enable.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-12a\

Flow Chart



4-x-2-encoder-flow-char-spartan

2 x 4 Decoder using conditional statement

Description :

In this program a 2 x 4 decoder has two 1- bit inputs and four 1- bit output. Additional control signals may be added such as enable.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-12b\

Flow Chart



2-x-4-decoder-flow-chart-spartan-3an

8 bit serial Shift register using behavioral description.

Description :

In these program a 8 bit shift register has one control line ( SW1) made ‘ON’ position to enable shift register . Every negative edge clock pulse 1 bit shifted alliteratively to right side output could be verified in point led’s on board.

Code Path :

PSSPIKE-FPGASP3AN\CODE\Ex-12c\

Flow Chart



8-bit-serial-shift-register-flow-chart-spartan-3an