You have no items in your shopping cart.

Subtotal: 0.00

User Manual for Spartan3 FPGA Starter Kit


The Spartan3 FPGA Starter Kit is a low-priced, compact prototyping board that can be used for rapid proof of concept or for educational environments. The board is based on the Spartan3 FPGA Starter Kit from Xilinx along with supporting circuitry to ease prototyping efforts. Designers can use the SPARTAN3 board for general FPGA prototyping, experimenting with multiple FPGA configuration techniques, and proving out low cost design methods.

Key Components and Features
  • 200,000-gate Xilinx Spartan3 FPGA Starter Kit in a 144-TQFP (XC3S200-4TQG144C)
       -4,320 logic cell equivalents
       -Twelve 18K-bit block RAMs (216K bits)
       -Twelve 18x18 hardware multipliers
       -Four Digital Clock Managers (DCMs)
       -Up to 97 user-defined I/O signals
  • 3-bit, 8-color VGA display port.
  • RS-232 Serial Port.
       -DB9 9-pin male connector with RS-232 transceiver/level translator
       -Uses straight-through serial cable to connect PC or workstation serial port
  • PS/2-connector( for mouse/keyboard interface) port
  • 8 Nos. Slide Switches for digital inputs
  • 8 nos. of Point LEDs for Digital outputs
  • 50 MHz crystal oscillator clock source
  • 3 Nos. 20-pin I/o connector for interface external peripherals modules
  • 40-pin Expansion connector for interface additional i/o modules
  • JTAG port for download user program through cable
  • 9V AC/DC power input through adapter
  • Power-on indicator LED
  • On-board 5V, 3.3V, 2.5V, and 1.2V regulators.
General block Diagram
General block Diagram
Jumper Details


Jumper and Main Switch Selection Details






     PROM Execution

     JTAG Executions

Connector Details
40-Pin Expansion Connector
40-Pin Expansion Connector
20pin – Box Connector
20pin – Box Connector
JTAG Connector
JTAG Connector
Power Supply

The external power can be AC or DC, with a voltage between (9V, 1A output) at 230V AC input. The Spartan3 FPGA Starter Kit produces +5V using an LM7805 voltage regulator, which provides supply to the peripherals.

USB socket meant for power supply and USB communication, user can select either USB or Ext power supply through SW1. Separate On/Off Switch (SW1) for controlling power to the board.








Power +5V ON -External through Adaptor    


Power +5V ON - Internal through USB


There are multiple voltages supplied on the Spartan-3 Evaluation Kit, 3.3V, 2.5V and 1.2V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The VCCAUX voltage input supplies power to Digital Clock Managers (DCMs) within the FPGA and supplies some of the I/O structures.

In specific, all of the FPGA’s dedicated configuration pins, such as DONE, PROG_B, CCLK, and the FPGA’s JTAG pins, are powered by VCCAUX. The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic. The board uses four discrete regulators to generate the necessary voltages.

On-board Peripherals

The Evaluation Kit comes with many interfacing options

  • 8-Nos. of Point LED’s (Digital Outputs)
  • 8-Nos. of Digital Inputs (Slide Switches)
  • UART for serial port communication through PC
  • JTAG Programmer
  • Clock Source
  • 3-bit, 8 Color VGA Interface
  • PS/2 Keyboard interface

Light Emitting Diodes
  • Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying pin’s digital states.
  • The SPARTAN3 Kit has 8 nos., of Point LEDs, connected with port pins (details tabulated below); the cathode of each LED connects to ground via a 220Ω resistor. To light an individual LED, drive the associated FPGA control signal to High.
 Light Emitting Diodes
Digital Inputs

  • This is another simple interface, of 8-Nos. of slide switch, mainly used to give an input to the port lines, and for some control applications also.
  • The SPARTAN3 Kit, slide switches (SW3-SW10) directly connected with FPGA I/O lines (details tabulated below), user can give logical inputs high through slide switches.

The switches are connected to +3.3V, in order to detect a switch state, by default lines are pull-downed through resistors. The switches typically exhibit about 2 ms of mechanical bounce and there is no active de-bouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. A 10KΩ series resistor provides nominal input protection.

Digital Inputs

RS-232 Communication(USART)

USART stands for Universal Synchronous Asynchronous Receiver Transmitter.FPGA SPARTAN3 Kit provides an RS232 port that can be driven by the Spartan-3 FPGA. A subset of the RS232 signals is used on the Spartan 3 kit to implement this interface (RxD and TxD signals).

  • RS-232 communication enables point-to-point data transfer. It is commonly used in data acquisition applications, for the transfer of data between the microcontroller/FPGA and a PC.
  • The voltage levels of a FPGA and PC are not directly compatible with those of RS-232, a level transition buffer such as MAX3232 be used.




DB-9 Connector


FPGA Lines

Serial Port Section







 JTAG Programmer

The FPGASP3 Kit includes a JTAG programming and debugging chain. Pantech JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector to 6 pin female header connector. The JTAG cable connect directly to the parallel port of a PC and to a standard 6 pin JTAG programming header in the kit, can program a devices that have a JTAG voltage of 1.8V or greater.



6-Pin Header

JTAG Signals


FPGA Lines






















The Pantech low-cost parallel port to JTAG cable fits directly over the header stake pins, as shown in above figure. When properly fitted, the cable is perpendicular to the board. Make sure that the signals at the end of the JTAG cable align with the labels listed on the board. The other end of the Pantech cable connects to the PC’s parallel port. The Pantech cable is directly compatible with the Xilinx iMPACT software

Clock Source

The FPGA SPARTAN3 Kit has a dedicated 50 MHz series clock oscillator source and an optional socket for another clock oscillator source.





FPGA Lines

Crystal Oscillator






VGA Interface

The FPGA SPARTAN3 Kit includes a VGA display port through DB15 connector, Connect this port directly to most PC monitors or flat-panel LCD displays using a standard monitor cable As shown in table, the Spartan-3 FPGA controls five VGA signals: RED (R) its 1ST pin in connector, GREEN (G) its 2nd pin, BLUE (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all available on the VGA connector.



VGA Signals


FPGA Lines




Vertical Sync(VS)


Horizontal Sync(HS)









Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Drive the R, G, and B signals High or Low to generate the eight possible colors shown in below table.






































VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 modes. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics

Signal Timing for a 60Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel by- pixel basis.

Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom.

As shown in below figure, information is only displayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

The size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller indicates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the

Signal Timing for a 60Hz, 640x480 VGA Display

correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location.

The Spartan3 FPGA Starter Kit uses three bits per pixel, producing one of the eight possible colors shown in above table. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel.

The VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range.

The number of horizontal lines displayed at a given refresh frequency defines the horizontal “retrace” frequency.

PS/2 Interface

The FPGA SPARTAN3 Kit includes a PS/2 port and the standard 6-pin mini-DIN connector, labeled U11 on the board. User can connect PS/2 Devices like keyboard, mouse to the FPGA SPARTAN3 Kit. PS/2’s DATA (P8) and CLK (P10) lines connected to SPARTAN3 FPGA I/O Lines.

 PS/2 Interface

PS/2 Interface

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the Keyboard.

The PS/2 bus timing appears as shown in above figure. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. The attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.


The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A ps/2-style keyboard uses scan codes to communicate key press data nearly all keyboards in use today are ps/2 style. Each key has a single, unique scan code that is sent whenever the corresponding key is pressed.

The scan codes for most keys appear in below figure. If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends an “f0” key-up code, followed by the scan code of the released key. the keyboard sends the same scan code, regardless if a key has different shift and non-shift characters and regardless whether the shift key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an “e0” ahead of the scan code and furthermore, they might send more than one scan code. When an extended key is released, an “e0 f0” key-up code is sent, followed by the scan code.


The host can also send commands and data to the keyboard. Below figure provides a short list of some often-used





Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs


Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”.


Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after which the host sends a second byte to set the repeat rate.


Resend. Upon receiving a resend command, the keyboard resends the last scan code sent


Reset. Resets the keyboard

 The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state, Because the host is the bus master, the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit.
Board Layout

board Layout