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User Manual for Spartan3 FPGA Image Processing Board

Spartan3 FPGA Image Processing Board

Introduction

The Spartan3 FPGA Image Processing Board provides a powerful, self-contained development platform for designs targeting the new Spartan-3 FPGA from Xilinx. It features a 200K gate Spartan-3, on-board I/O devices, and 1MB fast asynchronous SRAM, making it the perfect platform to experiment with any new design, from a simple logic circuit to an embedded processor core. The board also contains a Platform Flash JTAG-programmable ROM, so designs can easily be made non-volatile. The Spartan-3 Starter Board is fully compatible with all versions of the Xilinx ISE tools, including the free Web Pack. The board ships with a power supply, and a programming cable.


Package Contents

  • Xilinx Spartan3 XC3S200 FPGA Kit
  • Serial Port Cable (DTE)
  • JTAG Download Cable
  • Printed User Manual
  • 5V Power AC Adaptor
  • LCD module
  • CD contains
    a) Software
    b) Example Programs
    c) User Manual
    d) Simple Projects

Learning Xilinx FPGA and ISE Development Software Basics

The Spartan-3 EDK Board provides a powerful, self-contained development platform for designs targeting the new Spartan-3 FPGA from Xilinx. It features a 200K gate Spartan-3, on-board I/O devices, and 1MB fast asynchronous SRAM, making it the perfect platform to experiment with any new design, from a simple logic circuit to an embedded processor core. The board also contains a Platform Flash JTAG-programmable ROM, so designs can easily be made non-volatile.


Components placement

tyro-plus-spartan3-edk-board

Figure 1. PS – TYRO PLUS SPARTAN3 (EDK) Board Components placement top view

Block Diagram

xilinx-spartan3advanced-development-board

Figure 2. Xilinx Spartan3Advanced Development Board Block Diagram

Power Distribution
AC Wall Adapter

The Spartan3FPGA Lab Kit includes an international-ready AC wall adapter that produces a +5V DC output. Connect the AC wall adapter to the barrel connector along the left edge of the board, indicated as in Figure 3. To disconnect power, switch off the power switch. The power indicator LED, as shown in Figure 3, lights up when power is properly applied to the board. The AC wall adapter operates from 100V to 240V AC input, at 50 or 60 Hz.

Voltage Regulators

There are Overall, the 5V DC switching power adapter that connects to AC wall power powers the board. A 3.3V regulator, powered by the 5V DC supply, provides power to the inputs of the 2.5V and 1.2V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The VCCAUX voltage input supplies power to Digital Clock Managers (DCMs) within the FPGA and supplies some of the I/O structures. In specific, all of the FPGA’s dedicated configuration pins, such as DONE, PROG_B, CCLK, and the FPGA’s JTAG pins, are powered by VCCAUX. The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic. The board uses three discrete regulators to generate the necessary oltages. However, various power supply vendors are developing integrated solutions specifically for Spartan-3 FPGAs.

power-supply-tyro-plus

Figure 3. Power Supply


On-board Peripherals

The Spartan3FPGA Lab Kit comes with many interfacing options

  • 2 Nos. of Seven-segment display
  • 8-Nos. of Toggle switches (Digital Inputs)
  • 4-Nos. of Push Button (Digital Inputs)
  • 8-Nos. of Point LED’s (Digital Outputs)
  • 2x16 Character LCD
  • UART for serial port communication through PC
  • PS/2 keyboard Interface
  • 3-Bit VGA Interface
Seven Segment Display

The Spartan3 FPGA Kit has a two-character, seven-segment LED display controlled by FPGA user-I/O pins, as shown in Figure 4. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each FPGA pin connected to the LED display is shown in Table 1. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.

seven-segment-display--tyro-plus

Figure 4. Seven-segment display connections from Spartan3FPGA Lab Kit

Table 1. Seven-segment display connections to the FPGA pins

 


Segment

FPGA PIN

A

P82

B

P83

C

P84

D

P85

E

P86

F

P87

G

P89

DP

P90

 
Table 2. Digit Enable (Anode Control) Signals (Active Low)

Anode Control

FPGA PIN

AN1

P76

AN0

P77

 

The LED control signals are time-multiplexed to display data on two characters. Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low. Through persistence of vision, the human brain perceives that all four characters appear simultaneously, similar to the way the brain perceives a TV display.

This “scanning” technique reduces the number of I/O pins required for the four characters. In case an FPGA pin were dedicated for each individual segment, then 32 pins are required to drive four 7-segment LED characters. The scanning technique reduces the required I/O down to 12 pins. The drawback to this approach is that the FPGA logic must continuously scan data out to the displays—a small price to save 20 additional I/O pins.

Table 3. Display Characters and Resulting LED Segment Control Values

 

Character

a

b

c

d

e

f

g

1

1

0

0

1

1

1

1

2

0

0

1

0

0

1

0

3

0

0

0

0

1

1

0

4

1

0

0

1

1

0

0

5

0

1

0

0

1

0

0

6

0

1

0

0

0

0

0

7

0

0

0

1

1

1

1

8

0

0

0

0

0

0

0

9

0

0

0

0

1

0

0

A

0

0

0

1

0

0

0

B

1

1

0

0

0

0

0

C

0

1

1

0

0

0

1

D

1

0

0

0

0

1

0

E

0

1

1

0

0

0

0

F

0

1

1

1

0

0

0

 
Example Code

To see the demo result, click on ISE icon inside Seven Segment folder of the CD.

Hardware Settings

Place Jumper at J5 (7SEG) to enable supply to seven segment display.

hardware-settings
Digital Inputs Toggle Switch

The Spartan3 FPGA Kit has eight slide switches, indicated as in Figure 5. The switches connect to an associated FPGA pin, as shown in Table 4. A detailed schematic appears in Figure 5.

slide-switches--tyro-plus

Figure 5. Slide switches connections from Spartan3FPGA Lab Kit

Table 4. FPGA Connections to Slide Switches

Switch

1

2

3

4

5

6

7

8

FPGA pin

P99

P100

P102

P103

P104

P105

P107

P108

  

When in the UP or ON position, a switch connects the FPGA pin to VCCO, a logic High. When DOWN or in the OFF position, the switch connects the FPGA pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. A 10KΩ series resistor provides nominal input protection.

Example Code

To see the demo result, click ISE icon inside Digital Input Switch folder of the CD

Light Emitting Diodes

Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying pin’s digital states. The Spartan3 FPGA Lab Kit has eight LEDs located above the push button switches, indicated by in Figure 6.

point-led-interface-tyro-plus

Figure 6. Point LED interface from Spartan3FPGA Lab Kit

Table 5. FPGA connections to the LEDs

LED

D1

D2

D3

D4

D5

D6

D7

D8

FPGA   pin

P82

P83

P84

P85

P86

P87

P89

P90

 

The cathode of each LED connects to ground via a 220 ohm Ω resistor. To light an individual LED, drive the associated FPGA control signal High, which is the opposite polarity from lighting one of the 7-segment LEDs.

Example Code

To see the demo result, click on ISE icon inside LED folder of the CD.

Hardware Settings

Place Jumper at J6 (LED) to enable supply to LED.

hardware-settings-tyro-plus
2x16 Graphical LCD

The Spartan3 FPGA Lab Kit prominently features a 2x16 liquid crystal display (LCD).The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA to meet the 5V TTL voltage level requirements. The character LCD drives the data lines when LCD_RW is high. Most applications treat the LCD as a write-only peripheral and never read from the display.

Table 6. LCD Connection to FPGA

Signal

FPGA PIN

R/W

P79

RS

P78

E

P80

D0

P82

D1

P83

D2

P84

D3

P85

D4

P86

D5

P87

D6

P89

D7

P90

 
lcd-connections-tyro-plus

Figure 7. LCD connections from Spartan 3 FPGA Kit


Example Code

To see the demo result, click on ISE icon inside LCD folder of the CD.

Hardware Settings

Place Jumper at J7 (LCD) to enable supply to LCD.

hardware-settings-tyro-edk
4 Push Buttons

The Spartan3 FPGA Kit has four contact push button switches, indicated as in Figure 8.

push-button-interface-tyro-plus

Figure 8. Push Button interface from Spartan3 FPGA Kit

Table 7. FPGA Connections to Push Button

Switch

Sw3

Sw5

Sw6

Sw7               (Soft Reset)

FPGA   pin

P68

P69

P70

P98

Example Code

To see the demo result, click ISE icon inside Push Button folder of the CD

RS-232 Serial Port

UART stands for Universal Asynchronous Receiver Transmitter. The FPGA Kit provides an RS232 port that can be driven by the Spartan3 FPGA. A subset of the RS232 signals is used on the Spartan3 FPGA Lab Kit to implement this interface (RD and TD signals). The FPGA Kit provides female DB-9 connector, labeled P2. This board utilizes the Maxim Instruments MAX3232 RS232 driver for driving the RD and TD signals. The user provides the RS232 UART code, which resides in the Spartan3 FPGA.

Table 8. RS232 signals and their pin assignments to the Spartan3 FPGA

Connector Name

Signals

FPGA PIN

P2(DTE)

TXD

P63

P2(DTE)

RXD

P60

 

detailed-schematic-of-fpga-interface-with-rs232

Figure 9. Detailed schematic of FPGA Interface with RS232


Example Code

To see the demo result, click on ISE icon inside RS232 folder of the CD.

PS/2 Interface

The Spartan3 FPGA Kit includes PS/2 port for mouse/keyboard interface and it is the standard 6-pin mini-DIN connector, labeled U12 on the board. Figure 10 shows the PS/2 connector, and Table 9 shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA.

Table 9. PS/2 Interface with Spartan3FPGA

Connector Name

Signals

FPGA PIN

PS2

DATA

P73

PS2

CLK

P74

 
Table 10. PS/2 Bus Timing

Symbol

Parameter

MIN

MAX

Tck

Clock High or Low

Time

30us

50us

Tsu

Data to Clock

Setup

Time

5us

20us

Thld

Clock to data

Hold

Time

5us

20us

 

ps-2-bus-timing-waveforms-tyro-plus

Figure 10. PS/2 Bus Timing Waveforms

ps-2-interface-with-spartan3fpga

Figure 11. PS/2 Interface with Spartan3FPGA

Both the PC mouse and the keyboard uses the two-wire PS/2 serial bus to communicate with a host device, the Spartan3 FPGA in this case. The PS/2 bus includes both clock and data. Both the mouse and the keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard.

The PS/2 bus timing appears in Table 10 and Figure 15 the clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 10, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.

Keyboard

The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A ps/2-style keyboard uses scan-codes to communicate key press data. Nearly all keyboards in use today are ps/2 style. Each key has a single, unique scan-code that is sent whenever the corresponding key is pressed. The scan-codes for most keys appear in Figure 11. If the key is pressed and held, the keyboard repeatedly sends the scan-code every 100 ms or so. When a key is released, the keyboard sends an “f0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different SHIFT and non-SHIFT characters and regardless whether the SHIFT key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an “e0” ahead of the scan-code and furthermore, they might send more than one scan code. When an extended key is released, an “e0 f0” key-up code is sent, followed by the scan code.

keyboard-spartan-3-primer

Figure 16. PS\2 style scan-code keyboard

The host can also send commands and data to the keyboard. Table 11 provides a short list of some often-used commands.

Table 11. Common PS/2 Keyboard Commands

Command

Description

ED

Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs

EE

Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”.

F3

Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after which the host sends a second byte to set the repeat rate.

FE

Resend. Upon receiving a resend command, the keyboard resends the last scan code sent

FF

Reset. Resets the keyboard

 

The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state, because the host is the bus master, and the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 10.

Mouse

A mouse generates a clock and data signal when moved; otherwise, these signals remain High, indicating the idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in Figure 12. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.

ps-2-mouse-transaction

Figure 17. PS/2 Mouse Transaction

A PS/2-style mouse employs a relative coordinate system (see Figure 18), wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving it down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a ‘1’ indicates a negative value.

mouse-uses-a-relative-coordinate-system

Figure 18. The Mouse Uses a Relative Coordinate System to Track Movement

The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeats approximately every 50 ms. The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated mouse button is being pressed.

Voltage Supply

The PS/2 port on the Spartan3 FPGA Lab Kit is powered by 5V. Although the Spartan3 FPGA is not a 5V-tolerant device, it can communicate with a 5V device using series current-limiting resistors, as shown in Figure 16.

Example Code

To see the demo result, click on ISE icon inside PS/2 folder of the CD.

VGA Display Port

The Spartan3 FPGA Kit includes a VGA display port and DB15 connector, as indicated in Figure 14. You can connect this port directly to most PC monitors or flat-panel LCD displays using a standard monitor cable.

vga-interface-tyro-plus

Figure 14. VGA interface from Spartan3 kit

As shown in Figure 20, the Spartan3 FPGA controls five VGA signals: Red (R) its 1st pin in connector, Green (G) its 2nd pin, Blue (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all available on the VGA connector. The FPGA pins that drive the VGA port appear in Table 12. A detailed schematic is in Figure 20.

Table 12. FPGA connections to the VGA

Signals

FPGA PIN

Horizontal Sync (Hs)

P93

Vertical Sync (Vs)

P92

Red

P97

Green

P96

Blue

P95

 

Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Drive the R, G, and B signals High or Low to generate the eight possible colors shown in Table 13.

Table 13. 3-Bit Display Color Codes

RED

GREEN

BLUE

RESULTING COLOR

0

0

0

BLACK

0

0

1

BLUE

0

1

0

GREEN

0

1

1

CYAN

1

0

0

RED

1

0

1

MAGENTA

1

1

0

YELLOW

1

1

1

WHITE

 

VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 modes. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics

Signal Timing for a 60Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 21, information is only displayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

vga-interface-spartan-3-primer

Figure 17. Illustration of the working of a VGA display

The size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller indicates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The Spartan3 Starter Kit board uses three bits per pixel, producing one of the eight possible colors shown in Table 14. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. As shown in Figure 15, the VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal “retrace” frequency.

Example Code

To see the demo result, click on ISE icon inside VGA folder of the CD.

JTAG Programming/Debugging Ports

The Spartan3 FPGA Lab kit includes a JTAG programming and debugging chain. Additionally, there are two JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 6-pin female header connector. The JTAG cable connects directly to the parallel port of a PC and to a standard 6-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater.


jtag-connection-tyro-plus

Figure 16. JTAG connection with Spartan3 FPGA

This JTAG header consists of 0.1-inch stake pins, located toward the top edge of the board, directly below the two expansion connectors. The Pantech low-cost parallel port to JTAG cable fits directly over the header stake pins, as shown in Figure 16. When properly fitted, the cable is perpendicular to the board. You must make sure that the signals at the end of the JTAG cable align with the labels listed on the board. The other end of the Pantech cable connects to the PC’s parallel port. The Pantech cable is directly compatible with the Xilinx impact software.

xilinx-impact-software
Clock Source

The Spartan3 FPGA Lab Kit has two dedicated 50 MHz series clock oscillator source and an optional socket for another clock oscillator source. Figure 17 provides a detailed schematic for the clock sources.

The oscillator socket, indicated as in Figure 17, accepts oscillators in an 8-pin DIP footprint.

Table 20. Clock Oscillator Sources

Connector Name

Signals

FPGA PIN

Clock

DATA

P55

 

clock-source-connections--tyro-plus

Figure 17. Clock source connections from Spartan3FPGA Lab Kit

SRAM

Synchronous The Spartan®-3 FPGA board has a megabyte of fast asynchronous SRAM, surface-mounted to the backside of the board. The memory array includes two 256Kx16 SRAM devices, as shown in Figure 2-1.

The SRAM array forms either a single 256Kx32 SRAM memory or two independent 256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable (OE#), and address (A[17:0]) signals. However, each device has a separate chip select enable (CE#) control and individual byte-enable controls to select the high or low byte in the 16-bit data word, UB and LB, respectively.

The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions. However, it alternately provides high-density data storage for a variety of applications, such as digital signal processing (DSP), large data FIFOs, and graphics buffers.

SRAM Address Bus Connection

Signals

FPGA Pins

A0

P1

A1

P2

A2

P4

A3

P5

A4

P6

A5

P7

A6

P8

A7

P10

A8

P11

A9

P12

A10

P13

A11

P14

A12

P15

A13

P17

A14

P18

A15

P20

A16

P21

A17

P23

 
Write Enable and Output Enable Control Signals

Signals

FPGA Pins

OE#

P24

WE#

P25

SRAM Data Signals, Chip Enables, and Byte Enables

The data signals, chip enables, and byte enables are dedicated connections between the FPGA and SRAM. Table 2-3 shows the FPGA pin connections to the SRAM designated IC10 in Figure A-8. Table 2-4 shows the FPGA pin connections to SRAM IC11. To disable an SRAM, drive the associated chip enable pin High.

 

Signals

FPGAPins

D0

P27

D1

P28

D2

P30

D3

P31

D4

P32

D5

P33

D6

P35

D7

P36

D8

P41

D9

P44

D10

P46

D11

P47

D12

P50

D13

P51

D14

P52

D15

P53

CE1

P56

CE2

P137

UB1

P57

LB1

P59

UB2

P140

LB2

P141

 

sram-interface-tyro-plus

Figure 24. SRAM Interface with Spartan3FPGA

Example Code

To see the demo result, click on ISE icon inside SRAM folder of the CD.

Spartan3 FPGA
Introduction

The purpose of this daughter board is to integrate all the necessary components for using a FPGA, but without being targeted on a special application. The board provides 138 data pins to the user, who can use them as inputs, outputs or both. The main component of the daughter board is Spartan 3 or Spartan 3E FPGA. The following figure elaborates the denotation.

elaborates-the-denotation

Device Part Marking

device-part-marking 

The second important component on this board is the XCF04S-PROM, in which you can store a bit-file. The FPGA can be programmed directly from the PROM or through the JTAG connection. If the PROM-Boot option is enabled, the FPGA will be programmed out of the PROM when the power is turned on.

 

The input voltage (VCC) of the board is 3.3V. The voltage converter LT1086CT from Linear Technology provides the 1.8V Core-Voltage for the FPGA.

 

Also located on the board are: push buttons (Reset, Program, and User), 1 oscillator inputs from base board and the JTAG connector. With jumpers, you can enable or disable the PROM-Boot option and the pre-configuration pull-ups.

 

An overview of the Daughter Board SPARTAN-3 is presented in the following table.

 

Table 25. An overview of the Daughter Board SPARTAN-3

Device

Logic Cells

Typical System Gate Range

CLB Array   (R X C)

Total CLBs

Maximum Available User I/O Pins

Distributed RAM Bits

K = 1024

Block Ram Bits

DCMs

XC3S200ETQ144

4,320

200K

24 X 20

480

97

30K

216K

4

XC3S500EPQ208

10,476

500K

46 X 34

1,164

158

73K

360K

4

 

A general overview of the FPGA architecture is presented in the following figure.

general-overview-of-the-fpga-architecture

Figure 31. A general overview of the FPGA architecture

Dedicated Pins

The complete pin-out table of the Spartan 3 is described in Table 26. The following tables describe about the dedicated pins of the FPGA.

Table 26. Pin out table of Spartan3: XC3S200TQ144

Pin

Function

71

DONE

143

PROGRAM#

58

INIT#

72

CCLK

109

TDO

110

TCK

111

TMS

144

TDI

142

HSWAP_ENABLE

65

DO

38

M0

37

M1

39

M2

 
Table 27. Supply pins of Spartan3: XC3S200TQ144

GND

94,88,9,16,22,29,45,42,81,101,114,136,139,117,64,69

VCC (3.3V)

75,91,106,3,19,34,138,126,115,54,43,66

VCCINT (1.8V)

133,49,121,61

VCCAUX (2.5V)

48,62,134,120

 
Table 28. Pin description of Spartan3: XC3S200TQ144

Pin

Function

DONE

High when programming of the FPGA was successful

CCLK

Configuration Clock Pin

TCK, TDI, TDO, TMS

JTAG signals

M0, M1, M2

Define the configuration mode. With this board the user can choose between Boundary-Scan Mode and Master Serial Mode (PROM-Boot enabled) or only Boundary-Scan Mode (PROM-Boot disabled)

INIT#

Low while clearing the configuration memory

Configuration PROM
Table 29. Pin description of Spartan3: XC3S200TQ144

Jumper Setting

Description

JTAG

The FPGA boots from Platform Flash. No additional data storage is available

PROM

The FPGA boots from Platform Flash, which is permanently enabled. The FPGA can read additional data from Platform Flash.

 
JTAG OPTION

For most applications, this is the default jumper setting. As shown in Figure 32, the Platform Flash is enabled only during configuration when the FPGA’s DONE pin is Low. When the DONE pin goes high at the end of configuration, the Platform Flash is disabled and placed in low-power mode.

enabling-platform-flash

Figure 32. Enabling Platform Flash

 

PROM READ OPTION

The Spartan-3 FPGA Lab Kit includes a 4Mbit Platform Flash configuration PROM. The XC3S400 FPGA on the board only requires slightly less than 1Mbit for configuration data. The remainder of the Platform Flash is available to store other non-volatile data, such as revision codes, serial numbers and coefficients. To allow the FPGA to read from Platform Flash after configuration, the JP3 jumper must be properly positioned as shown in Figure 33. When the jumper is in this position, the Platform Flash is always enabled.

enabling-platform-flash-promFigure 33. Enabling Platform Flash

NONE OPTION

If the JP3 jumper is removed, then the Platform Flash and FPGA are disabled.

PROG RST Push Button

The PROG RST push button forces the FPGA to reconfigure from the selected configuration memory source. Press and release this button to restart the FPGA configuration process at any time.

DONE Pin LED

The DONE pin LED lights whenever the FPGA is successfully configured. If this LED is not lit, then the FPGA is not configured.

Appendix I