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Introduction

FPGASP3 Kit (DPK) is an exclusive general-purpose kit for the SPARTAN family. The intention of the design is to endorse the engineers and scholars to exercise and explore the capabilities of FPGA architectures with many interfacing modules on board point LEDs, Slide switches, Traffic light, LCD, 7-Seg, UART, VGA, and PS/2 with ease to create a stand-alone versatile test platform.

Packages

Spartan3 Development Kit (XC3S200)

☞Serial Port Cable

☞JTAG Programming Cable

☞Printed User Manual

☞CD contains oSoftware (Programmers, ISE) oExample Programs oUser Manual

Key Components and Features

On-Chip Features

200,000-gate Xilinx Spartan 3 FPGA in a 144-TQFP (XC3S200-4TQG144C)

☞4,320 logic cell equivalents

☞Twelve 18K-bit block RAMs (216K bits)

☞Twelve 18x18 hardware multipliers

☞Four Digital Clock Managers (DCMs)

☞Up to 97 user-defined I/O signals

On-Board Features

☞8 Nos. Slide Switches for digital inputs

☞8 nos. of Point LEDs for Digital outputs

2x16 Character LCD interface

☞4 Nos. 7-segment LED CA display

☞2 Nos. of 5V SPDT Relay with termination.

4x4 Matrix Keypad interface

☞4-Way Traffic Light controller Module

☞Stepper motor Driver interface

DC Motor interface controlled by PWM

☞3-bit, 8-color VGA display port.

RS-232 Serial Port.

PS/2-connector( for mouse/keyboard interface) port

128x64 GLCD Module Interface (Optional)

Serial EEPROM (Optional)

I2C Real Time Clock with battery back-up (Optional)

1-Wire Digital Temperature Sensor (Optional)

☞50 MHz crystal oscillator clock source

☞20-pin I/o connector for interface external peripherals modules

☞JTAG port for download user program through cable

☞9V AC/DC power input through adapter

☞On-board 5V, 3.3V, 2.5V, and 1.2V regulators.

 

General Block Diagram



General Block Diagram

 

Jumper & Switch Details

Stepper / Relay

JP5

Jumper & Switch Details

Internal Supply (+5V)

External Supply(+5V)

DC Motor

JP6

Jumper & Switch Details

Internal Supply (+5V)

External Supply(+5V)

Buzzer (P5)

JP7

Jumper & Switch Details

Enable Buzzer

Disable Buzzer

 

Switch Details

Program Execution Mode Selection ( EXE MODE)

 

JTAG/PROM

J6

 Program Execution Mode Selection ( EXE MODE)

 

Execution through JTAG

 

Execution through PROM

 

GLCD / Traffic Light Selection

 

GLCD/Traffic

SW28

 GLCD / Traffic Light Selection

 

Select GLCD

 

Select TRAFFIC

 

+5V Power Selection

+5V Power Selection

 

Connector Details

20pin – Box Connector



20pin – Box Connector

 

JTAG Connector



JTAG Connector

Power Supply

The external power can be AC or DC, with a voltage between (9V, 1A output) at 230V AC input. The SPARTAN3 board produces +5V using an LM7805 voltage regulator, which provides supply to the peripherals.

USB socket meant for power supply and USB communication, user can select either USB or Ext power supply through SW1. Separate On/Off Switch (SW1) for controlling power to the board.

 

ON/OFF

SW2

Power Supply


Power +5V ON -External through Adaptor

 

Power +5V ON - Internal through USB

 

There are multiple voltages supplied on the Spartan-3 Evaluation Kit, 3.3V, 2.5V and 1.2V regulators. Similarly, the 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The VCCAUX voltage input supplies power to Digital Clock Managers (DCMs) within the FPGA and supplies some of the I/O structures.

In specific, all of the FPGA’s dedicated configuration pins, such as DONE, PROG_B, CCLK, and the FPGA’s JTAG pins, are powered by VCCAUX. The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse current. Finally, a 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic. The board uses four discrete regulators to generate the necessary voltages.

On-board Peripherals

The Development Kit comes with many interfacing options

☞8 Nos. Slide Switches for digital inputs

☞8 nos. of Point LEDs for Digital outputs

☞2x16 Character LCD interface

☞4 Nos. 7-segment LED CA display

☞2 Nos. of 5V SPDT Relay with termination.

4x4 Matrix Keypad interface

☞4-Way Traffic Light controller Module

Stepper motor Driver interface

DC Motor interface controlled by PWM

Buzzer Interface

UART for serial port communication through PC

GLCD | I2C EEPROM | RTC | 1-Wire Temp Sensor (Optional)

☞JTAG Programmer

☞Clock Source

☞3-bit, 8 Color VGA Interface

PS/2 Keyboard interface

Light Emitting Diodes

Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying pin’s digital states.

☞The FPGA SPARTAN3 KIT has 8 nos., of Point LEDs, connected with port pins (details tabulated below); the cathode of each LED connects to ground via a 330Ω resistor. To light an individual LED, drive the associated FPGA control signal to High.

 

Point LEDs

XC3S200 - Pins

LED Selection

DIGITAL OUTPUTS

LED-D9

P14

LED Selection

LED-D10

P15

LED-D11

P17

LED-D12

P18

LED-D13

P20

LED-D14

P21

LED-D15

P23

LED-D16

P24

 

Digital Inputs

☞This is another simple interface, of 8-Nos. of slide switch, mainly used to give an input to the port lines, and for some control applications also.

☞The FPGA SPARTAN3 KIT, slide switches (SW20-SW27) directly connected with FPGA I/O lines (details tabulated below), user can give logical inputs high through slide switches.

The switches are connected to +3.3V, in order to detect a switch state, by default lines are pull-downed through resistors. The switches typically exhibit about 2 ms of mechanical bounce and there is no active de-bouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. A 10KΩ series resistor provides nominal input protection.

 

Slide Switch

XC3S200 - Pins

Slide Switch Logic

DIGITAL INTPUTS

SW20

P25

Slide Switch Logic

SW21

P26

SW22

P27

SW23

P28

SW24

P30

SW25

P31

SW26

P32

SW27

P33

 

2x16 Char LCD Display

The 2x16 character LCD interface card with supports both modes 4-bit and 8-bit interface, and also facility to adjust contrast through trim pot. In 8-bit interface 11 lines needed to create 8-bit interface; 8 data bits (D0 – D7), three control lines, address bit (RS), read/write bit (R/W) and control signal (E). The LCD controller is a standard KS0070B or equivalent, which is a very well-known interface for smaller character based LCDs.



 2x16 Char LCD Display

 

7-Segment Display

The FPGASP3 Kit has a four-character, seven segments LED display controlled by FPGA user-I/O pins. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each FPGA pin connected to the LED display is shown in below table. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.

 

7-Segment

XC3S200-Pins

7-Segment Display

Digit Select

Digit - 1

P124

7-Segment Display

Digit – 2

P125

Digit – 3

P127

Digit - 4

P128

Segment Lines

Seg - a

P129

Seg – b

P130

Seg – c

P131

Seg – d

P132

Seg – e

P135

Seg – f

P137

Seg – g

P140

Seg – dp

P141

 

Make switch SW1 to ‘7SEG’ label marking position

 

4x4 Matrix keypad

Keypads arranged by matrix format, each row and column section pulled by high, all row lines and column lines connected directly by the i/o pins.

 

4x4 Matrix Keys

XC3S200-pins

Matrix Format

ROW

ROW-1

P85

Matrix Format

ROW-2

P86

ROW-3

P87

ROW-4

P89

COLUMN

COLUMN-1

P90

COLUMN-2

P92

COLUMN-3

P95

COLUMN-4

P96

 

Stepper Motor

The ULN2803A is a high-voltage, high-current Darlington transistor array. The device consists of eight NPN Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of each Darlington pair, 500 mA.

ULN2803 is used as a driver for port I/O lines, drivers output connected to stepper motor, connector provided for external power supply if needed.

 

Stepper Motor(5V)

XC3S200-Lines

Stepper Motor PWR Select

STEPPER MOTOR

COIL-A

P82

Stepper Motor PWR Select

COIL-B

P83

COIL-C

P99

COIL-D

P100

Make switch SW1 to SM/RL label

marking position.

Stepper Motor PWR Select
 

For Motor/relay designer get power from on-board (internal) or external supply through jumper JP5, by default JP5 pin 1&2 shorted

DC Motor

5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program.

 

DC Motor(5V)

XC3S200-Lines

DC Motor PWR Select

DC MOTOR

COIL-A

P82

DC Motor PWR Select

COIL-B

P83

ENA

P99

Make switch SW1 to SM/RL label

marking position.

DC Motor PWR Select
 

For DC Motor designer get power from on-board (internal) or external supply through jumper JP6, by default JP6 pin 1&2 shorted.

Relay Interface

ULN2803 is used as a driver for port I/O lines, drivers output connected to relay modules. Connector provided for external power supply if needed.

Relay Module :

FPGA SPARTAN3 pins (Realy1 – P59) and (Relay2-P60) for relay module,make port pins to high, relay will activated

 

RELAY SPDT

XC3S200-pins

RELAY Power Select

RELAY Modules

Relay-1

P59

RELAY Power Select

Relay-2

P60

Note:Relay selection make switch SW1 to SM/RL label marking position

 

For Motor/relay designer get power from on-board (internal) or external supply through jumper JP5, by default JP5 pin 1&2 shorted.

Buzzer Interface

5V continuous buzzer connected through FPGA’s I/O pins (P5), to enable buzzer place jumper JP7 at E label mark position.

Buzzer Module :

FPGA SPARTAN3 pins (Buzzer – P5), make port pins to high, buzzer will activated

 

5V Buzzer

XC3S200-pins

RELAY Power Select

Buzzer

Buzzer

P5

RELAY Power Select
 

Traffic Light Controller

Traffic light controller card consist of 12 Nos. point led arranged by 4Lanes. Each lane has Go (Green), Listen(Yellow) and Stop(Red) LED is being placed. Each LED has provided for current limiting resistor to limit the current flows to the LEDs.

LAN Direction

XC3S200-pins

LED’s

Traffic Light Controller

NORTH

P40

D19-Go

 


Traffic Light Controller

 


P36

D18-Listen

P35

D17-Stop

WEST

P46

D22-Go

P44

D21-Listen

P41

D20-Stop

SOUTH

P51

D25-Go

P50

D24-Listen

P47

D23-Stop

EAST

P56

D28-Go

P53

D27-Listen

P52

D26-Stop

Note : Make SW28 to “Traffic” label marking position

 

Peripherals Section - II

RS-232 Communication(USART)

USART stands for Universal Synchronous Asynchronous Receiver Transmitter. FPGA SPARTAN3 KIT provides an RS232 port that can be driven by the Spartan-3 FPGA. A subset of the RS232 signals is used on the Spartan 3 kit to implement this interface (RxD and TxD signals).

RS-232 communication enables point-to-point data transfer. It is commonly used in data acquisition applications, for the transfer of data between the microcontroller/FPGA and a PC.

☞The voltage levels of a FPGA and PC are not directly compatible with those of RS-232, a level transition buffer such as MAX3232 be used.

 

UART

DB-9 Connector

SPARTAN3

FPGA Lines

Serial Port Section

UART

TXD

P15

Serial Port Section

RXD

P14

 

Clock Source

The FPGA SPARTAN3 KIT has a dedicated 50 MHz series clock oscillator source and an optional socket for another clock oscillator source.

 

U18

Signal

SPARTAN3

FPGA Lines

Crystal Oscillator

Oscillator

50MHz

Clock

P55

Crystal Oscillator

 

JTAG Programmer

The FPGA SPARTAN3 Kit includes a JTAG programming and debugging chain. Pantech JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector to 6 pin female header connector. The JTAG cable connect directly to the parallel port of a PC and to a standard 6 pin JTAG programming header in the kit, can program a devices that have a JTAG voltage of 1.8V or greater.

 

6-Pin Header

JTAG Signals

SPARTAN3

FPGA Lines

JTAG Programmer

JTAG

Programmer

1

TMS

P111

2

TDI

P144

3

TDO

P109

4

TCK

P110

5

GND

 

6

VCC

 

The Pantech low-cost parallel port to JTAG cable fits directly over the header stake pins, as shown in above figure. When properly fitted, the cable is perpendicular to the board. Make sure that the signals at the end of the JTAG cable align with the labels listed on the board. The other end of the Pantech cable connects to the PC’s parallel port. The Pantech cable is directly compatible with the Xilinx iMPACT software.

VGA Interface

The FPGA SPARTAN3 KIT includes a VGA display port through DB15 connector, Connect this port directly to most PC monitors or flat-panel LCD displays using a standard monitor cable As shown in table, the Spartan-3 FPGA controls five VGA signals: RED (R) its 1ST pin in connector, GREEN (G) its 2nd pin, BLUE (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all available on the VGA connector.

DB-15

Connector

VGA Signals

SPARTAN3

FPGA Lines

VGA Port

DB-15 Connector

 

Vertical Sync(VS)

P6

Horizontal Sync(HS)

P7

Blue

P8

Green

P10

Red

P11

 

Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Drive the R, G, and B signals High or Low to generate the eight possible colors shown in below table.

RED

GREEN

BLUE

RESULTING COLOUR

0

0

0

BLACK

0

0

1

BLUE

0

1

0

GREEN

0

1

1

CYAN

1

0

0

RED

1

0

1

MAGNETA

1

1

0

YELLOW

1

1

1

WHITE



VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 modes. For more precise information or for information on higher VGA frequencies, refer to documents available on:

☞VESA website or other electronics Websites: Video Electronics Standards Association http://www.vesa.org

☞VGA Timing Information http://www.epanorama.net/documents/pc/vga_timing.html

Signal Timing for a 60Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel by- pixel basis.

Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom.

As shown in below figure, information is only displayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.

The size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller indicates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils, and it ensures that pixel or video data is applied to the electron guns at the



VGA Display

correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location.

The Spartan-3 Evaluation Kit uses three bits per pixel, producing one of the eight possible colors shown in above table. The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel.

The VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range.

The number of horizontal lines displayed at a given refresh frequency defines the horizontal “retrace” frequency.

PS/2 Interface

The FPGA SPARTAN3 KIT includes a PS/2 port and the standard 6-pin mini-DIN connector, labeled U11 on the board. User can connect PS/2 Devices like keyboard, mouse to the FPGA SPARTAN3 KIT. PS/2’s DATA (P8) and CLK (P10) lines connected to Spartan3 FPGA I/O Lines.

6PIN MINI Connector

PS/2

SPARTAN3

FPGA Lines

ps2 port select

U11

PS/2

DATA

P1

CLK

P2

 


ps2 serial

Both a PC mouse and keyboard use the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3 FPGA in this case. The PS/2 bus includes both clock and data. Both a mouse and keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the Keyboard.

The PS/2 bus timing appears as shown in above figure. The clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. The attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.

Keyboard

The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A ps/2-style keyboard uses scan codes to communicate key press data nearly all keyboards in use today are ps/2 style. Each key has a single, unique scan code that is sent whenever the corresponding key is pressed.

The scan codes for most keys appear in below figure. If the key is pressed and held, the keyboard repeatedly sends the scan code every 100 ms or so. When a key is released, the keyboard sends an “f0” key-up code, followed by the scan code of the released key. the keyboard sends the same scan code, regardless if a key has different shift and non-shift characters and regardless whether the shift key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an “e0” ahead of the scan code and furthermore, they might send more than one scan code. When an extended key is released, an “e0 f0” key-up code is sent, followed by the scan code.



Keyboard

Commands

The host can also send commands and data to the keyboard. Below figure provides a short list of some often-used