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User Manual for FPGA/CPLD Universal Development Board

Universal Development Board

Introduction

Universal Development Board is an exclusive general-purpose development kit for the Various FPGA and CPLD family. The intention of the design is to endorse the engineers and scholars to exercise and explore the capabilities of FPGA architectures with many protocol ease. It integrates on board GLCD, Traffic light Controller, UARTs, VGA, keypads, and Relay to create a stand-alone versatile test platform.


 
universal-development-drive-anode-input-low.jpg
Package Contents


Learning Universal Development Board

The Universal Development Board comes with a base board and multiple FPGA/CPLD top board. Base board includes several peripherals, power supply and supporting device circuitry. Systems can be configured with up to four I/O modules (Spartan 3 / Spartan 3E/XC95288XL/Cyclone 3). Universal Development Board provides a basic development platform for the FPGA device with all I/O available to the user. The device may be programmed in-circuit through the JTAG port from the PC. We meet all the basic specifications’ standards with this product. One can experience the ease in the experimentation of Xilinx and Altera series FPGA and CPLD with many of the external peripherals.


Components placement


universal-development-board-components

Figure 1. Universal Development Board Components placement


Block Diagram


universal-development-board-block-diagram
 
Figure 2. Universal Development Board Block Diagram

 
Power Distribution

AC Wall Adapter

The Universal Development Board includes an AC wall adapter that produces a +9V DC output. Connect the AC wall adapter to the barrel connector along the left edge of the board, indicated as in Figure. To disconnect power, switch off the power switch. The power indicator LED, as shown in Figure, lights up when power is properly applied to the board. The AC wall adapter operates from 100V to 240V AC input, at 50 or 60 Hz.


Voltage Regulators

There are multiple voltages supplied on the Universal Development Board: 5V, 3.3V, 2.5V and 1.2V regulators. The 3.3V regulator feeds all the VCCO voltage supply inputs to the FPGA’s I/O banks and powers most of the components on the board. The 2.5V regulator supplies power to the FPGA’s VCCAUX supply inputs. The VCCAUX voltage input supplies power to Digital Clock Managers (DCMs) within the FPGA and supplies some of the I/O structures. In specific, all of the FPGA’s dedicated configuration pins, such as DONE, PROG_B, CCLK, and the FPGA’s JTAG pins, are powered by VCCAUX. The FPGA configuration interface on the board is powered by 3.3V. Consequently, the 2.5V supply has a current shunt resistor to prevent reverse current. Finally, the 1.2V regulator supplies power to the FPGA’s VCCINT voltage inputs, which power the FPGA’s core logic. The board uses four discrete regulators to generate the necessary voltages. The 5V Regulator supplies power for Stepper Motor, DC Motor, Relays, GLCD and LCD.



universal-development-power-supply

Figure 3 . Power Supply



On-board Peripherals

The Universal Development Board comes with many interfacing options


  • 6 Nos. of Seven-segment display
  • 2 Nos. of Push Button
  • 16-Nos. of Toggle switches (Digital Inputs)
  • 16-Nos. of Point LED’s (Digital Outputs)
  • 2x16 Character LCD
  • 128x64 G LCD with Contrast adjusts
  • DC Motor driver circuit
  • 4x4 Matrix keypad
  • Relay / Stepper Motor driver circuit
  • Two UART for serial port communication through PC
  • PS/2 keyboard Interface
  • Traffic Light Controller
  • 3-Bit VGA Interface
  • Piezo Electric Buzzer
  • Reset switch

Seven Segment Display

The Universal Development Board has a six-character, seven-segment LED display controlled by FPGA user-I/O pins, as shown in Figure 4. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin name for each pin connected to the LED display is shown in Table 1. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.



universal-development-seven-segment-display

Figure 4Seven-segment display connections from



Table 1. Seven-segment display connections to the FPGA pins

 


Segment

PIN Name

A

SEGA

B

SEGB

C

SEGC

D

SEGD

E

SEGE

F

SEGF

G

SEGG

DP

SEGDP

 

 
Table 2. Digit Enable (Anode Control) Signals (Active Low)

 


Anode Control

PIN NAME

AN5

DIGIT6

AN4

DIGIT5

AN3

DIGIT4

AN2

DIGIT3

AN1

DIGIT2

AN0

DIGIT1

 

 

The LED control signals are time-multiplexed to display data on all six characters, as shown in Figure 5. Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low. Through persistence of vision, the human brain perceives that all six characters appear simultaneously, similar to the way the brain perceives a TV display.


This “scanning” technique reduces the number of I/O pins required for the six characters. In case an FPGA pin were dedicated for each individual segment, then 48 pins are required to drive four 7-segment LED characters. The scanning technique reduces the required I/O down to 14 pins. The drawback to this approach is that the FPGA logic must continuously scan data out to the displays—a small price to save 36 additional I/O pins.



universal-development-drive-anode-input-low

Figure 5. Drive Anode Input Low to Light an Individual Character



Table 3. Display Characters and Resulting LED Segment Control Values

 


Character

a

b

c

d

e

f

g

1

1

0

0

1

1

1

1

2

0

0

1

0

0

1

0

3

0

0

0

0

1

1

0

4

1

0

0

1

1

0

0

5

0

1

0

0

1

0

0

6

0

1

0

0

0

0

0

7

0

0

0

1

1

1

1

8

0

0

0

0

0

0

0

9

0

0

0

0

1

0

0

A

0

0

0

1

0

0

0

B

1

1

0

0

0

0

0

C

0

1

1

0

0

0

1

D

1

0

0

0

0

1

0

E

0

1

1

0

0

0

0

F

0

1

1

1

0

0

0

 

 
Example Code

To see the demo result, click on ISE icon inside Seven Segment folder of the CD.


Digital Inputs Toggle Switch

The Universal Development Board has 16-slide switches, indicated as in Figure 6. The switches connect to an associated pin name, as shown in Table 4. A detailed schematic appears in Figure 6.



universal-development-slide-switches

Figure 6.Slide switches connections from Spartan 3 FPGA Lab Kit



Table 4. Pin Connections to Slide Switches

 


SWITCH

1

2

3

4

5

6

7

8

Pin Name

Sw1

Sw2

Sw3

Sw4

Sw5

Sw6

Sw7

Sw8

SWITCH

9

10

11

12

13

14

15

16

Pin Name

Sw9

Sw10

Sw11

Sw12

Sw13

Sw14

Sw15

Sw16

 

 

When in the UP or ON position, a switch connects logic High. When DOWN or in the OFF position, the switch connects to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the FPGA design programmed on the board. A 10KΩ series resistor provides nominal input protection.


Example Code

To see the demo result, click on ISE icon inside Digital Input Switch folder of the CD.


Light Emitting Diodes

Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying pin’s digital states. The Universal Development Board has 16- LEDs located above the slide switches, indicated by in Figure 7.



point-led-interface-universal-development

Figure 7. Point LED interface from Universal Development Board



Table 5. Pin connections to the LEDs

 


LED

D1

D2

D3

D4

D5

D6

D7

D8

Pin Name

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

LED

D9

D10

D11

D12

D13

D14

D15

D16

Pin Name

LED9

LED10

LED11

LED12

LED13

LED14

LED15

LED16

 

 

The cathode of each LED connects to ground via a 220 ohm Ω resistor. To light an individual LED, drive the associated FPGA control signal High, which is the opposite polarity from lighting one of the 7-segment LEDs.


Example Code

To see the demo result, click on ISE icon inside LED folder of the CD.


Character 2 x 16 LCD

The Universal Development Board prominently features a 2-line by 16-character liquid crystal display (LCD). The Top board controls the LCD via the 8-bit data interface shown in Figure 8. Although the LCD supports an 8-bit data interface..


Voltage Compatibility

The character LCD is power by +5V. The FPGA I/O signals are powered by 3.3V. However, the FPGA’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the FPGA to meet the 5V TTL voltage level requirements. The character LCD drives the data lines when LCD_RW is high. Most applications treat the LCD as a write-only peripheral and never read from the display.


Table 6. Pin Connection to LCD Interface

 


Signal

PIN Name

R/W

LCD_RW

RS

LCD_RS

E

LCD_E

D0

LCD_D0

D1

LCD_D1

D2

LCD_D2

D3

LCD_D3

D4

LCD_D4

D5

LCD_D5

D6

LCD_D6

D7

LCD_D7

 


lcd-connections-from-universal-development

Figure 8. LCD connections from Universal Development Board



Example Code

To see the demo result, click on ISE icon inside LCD folder of the CD.


128 x 64 GLCD

The Universal Development Board has 128x64 GLCD. 14 pins are needed to create 8-bit interface; 8 data bits (DB0-DB7), two chip select line (CS1) and (CS2), address bit (R/S), read/write bit (R/W) and control signal (E) and Reset (RST). The GLCD controller is a standard S6B0108 or equivalent, which is a very well-known interface for Graphical based LCDs.



lcd-connections-from-universal-development

Figure 9.GLCD connections from Universal Development Board



Table 7. Pin Connection to GLCD Interface

 


Signal

PIN Name

R/W

GLCD_RW

RS

GLCD_RS

E

GLCD_E

D0

GLCD_D0

D1

GLCD_D1

D2

GLCD_D2

D3

GLCD_D3

D4

GLCD_D4

D5

GLCD_D5

D6

GLCD_D6

D7

GLCD_D7

CS1

GLCD_CS1

CS2

GLCD_CS2

 

 
Example Code

To see the demo result, click on ISE icon inside GLCD folder of the CD.


Traffic Light Controller

The Universal Development Board has Traffic light controller. It consists of 12 Nos. point led arranged by 4Lanes. Each lane has Go (Green), Listen(Yellow) and Stop(Red) LED is being placed. Each LED has provided for current limiting resistor to limit the current flows to the LEDs.




keyboard-interface-universal-development

Figure 9. Keyboard interface from Spartan 3 FPGA Lab Kit



Table 7. Pin Connections to Traffic light controller

 


DIRECTION

PIN NAME

NORTH

GO

GLCD_D2

LISTEN

GLCD_D3

STOP

GLCD_D4

WEST

 

GO

GLCD_D5

LISTEN

GLCD_D6

STOP

GLCD_D7

SOUTH

 

GO

GLCD_CS1

LISTEN

GLCD_CS2

STOP

GLCD_RS

EAST

GO

GLCD_RW

LISTEN

GLCD_D0

STOP

GLCD_D1

 

 
Example Code

To see the demo result, click on ISE icon inside Keypad folder of the CD.


4x4 Matrix keypad

The Universal Development Board has sixteen momentary-contact push button switches, indicated as in Figure 9.




keyboard-interface-4x4-matrix-keypad

Figure 10.Keyboard interface from Spartan 3 FPGA Lab Kit



Table 9. Pin Connections to Keypad

 


SWITCH

Col

Row

Pin Name

Col1

Col2

Col3

Col3

Row1

Row2

Row3

Row4

 

 
Example Code

To see the demo result, click


Stepper Motor and DC Motor Driver Section

The ULN2803A is a high-voltage, high-current Darlington transistor array. The device consists of eight npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of each Darlington pair is 500 mA. The Darlington pairs may be connected in Parallel for higher current capability. ULN2803 is used as a driver for port I/O lines. It is also used with source which drive more than 50mA current.5V DC Motor speed has controlled through PWM signal. Motor can run both clockwise/counter clockwise, Motor speed controlled by varying ENA (duty cycle) signal through program.




stepper-motor-and-dc-motor-drive-uni-dev

Figure 11.Stepper motor and DC motor drivers interface with Universal Development Board



Table 10. Pin Connections to Motor/Driver

Signals

PIN NAME

Stepper Motor Control A

STEP1

Stepper Motor Control B

STEP 2

Stepper Motor Control C

STEP 3

Stepper Motor Control D

STEP 4

Dc Motor PWM1

DC_PWM1

Dc Motor PWM2

DC_PWM2

Dc Motor Enable

DC_EN

 

 
Example Code

To see the demo result, click on ISE icon inside Stepper Motor folder of the CD.


Relay Section

In Universal Development Board two SPDT relays are used. Both the relays operate on 5V DC. The outputs of both the terminals of the relay are taken out on the connecter to connect the external circuitry.

schematic showing the relay connections

Figure 12. Schematic showing the relay connections



Table 11. Pin Connections to Relay/Driver

 


Signals

PIN NAME

Relay1

Rly1

Relay2

Rly2

 

 
Example Code

To see the demo result, click on ISE icon inside Relay folder of the CD.


Buzzer Section

In Universal Development Board 5V continuous buzzer is used. To enable buzzer place jumper J11 at E label mark position.




schematic-showing-the-relay-universal-development

Figure 13. Schematic showing the relay connections



Table 11. Pin Connections to Relay/Driver

 


Signals

PIN NAME

Buzzer

Buzzer

 

 
Example Code

To see the demo result, click on ISE icon inside Buzzer folder of the CD


RS-232 Serial Port

USART stands for Universal Synchronous Asynchronous Receiver Transmitter. Universal Development Board supports both types of communication. The Universal Development Board provides an RS232 port that can be driven by the top board FPGA. A subset of the RS232 signals is used on the Kit to implement this interface (RD and TD signals). The Universal Development Board provides 2- female connector DB-9 connector, labeled P1 and P2. This board utilizes the Maxim Instruments MAX3232 RS232 driver for driving the RD and TD signals.


Table 8. RS232 signals and their pin assignments to the Spartan-3 FPGA

 



Connector Name

Signals

FPGA PIN

P1

TXD0

UART_TXD0

RXD0

UART_RXD0

P2

TXD1

UART_TXD1

RXD1

UART_RXD1

 



detailed-schematic-of-universal-development


Figure 14. Detailed schematic of Universal Development Board Interface with RS232



Example Code

To see the demo result, click ISE icon inside RS232 folder of the CD.


PS/2 Interface

The Universal Development Board includes PS/2 mouse/keyboard port and the standard 6-pin mini-DIN connector, labeled J3 on the board. Figure 16 shows the PS/2 connector, and Table 9 shows the signals on the connector. Only pins 1 and 5 of the connector attach to the FPGA.


Table 9. PS/2 Pin Connection with Universal Development Board

 


Signals

PIN NAME

DATA

PS2_DATA

CLK

PS2_CLK

 

Table 10. PS/2 Bus Timing

 


Symbol

Parameter

MIN

MAX

Tck

Clock High or Low

Time

30us

50us

Tsu

Data to Clock

Setup

Time

5us

20us

Thld

Clock to data

Hold

Time

5us

20us

 



ps-2-bus-timing-waveforms


Figure 15. PS/2 Bus Timing Waveforms




ps-2-interface-with--universal-development

Figure 16. PS/2 Interface with Universal Development Board



Both the PC mouse and the keyboard uses the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3E FPGA in this case. The PS/2 bus includes both clock and data. Both the mouse and the keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard.The PS/2 bus timing appears in


Table 10 and Figure 15 the clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 16, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.


Keyboard

The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A ps/2-style keyboard uses scan-codes to communicate key press data. Nearly all keyboards in use today are ps/2 style. Each key has a single, unique scan-code that is sent whenever the corresponding key is pressed. The scan-codes for most keys appear in Figure . If the key is pressed and held, the keyboard repeatedly sends the scan-code every 100 ms or so. When a key is released, the keyboard sends an “f0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different SHIFT and non-SHIFT characters and regardless whether the SHIFT key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an “e0” ahead of the scan-code and furthermore, they might send more than one scan code. When an extended key is released, an “e0 f0” key-up code is sent, followed by the scan code.




keyboard-spartan-3-primer

Figure 16. PS\2 style scan-code keyboard




The host can also send commands and data to the keyboard. Table 11 provides a short list of some often-used commands.


Table 11. Common PS/2 Keyboard Commands

 


Command

Description

ED

Turn on/off Num Lock, Caps Lock, and Scroll Lock LEDs

EE

Echo. Upon receiving an echo command, the keyboard replies with the same scan code “EE”.

F3

Set scan code repeat rate. The keyboard acknowledges receipt of an “F3” by returning an “FA”, after which the host sends a second byte to set the repeat rate.

FE

Resend. Upon receiving a resend command, the keyboard resends the last scan code sent

FF

Reset. Resets the keyboard

 

 

The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state, because the host is the bus master, and the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 15.


Mouse

A mouse generates a clock and data signal when moved; otherwise, these signals remain High, indicating the idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in Figure . Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.




ps-2-mouse-transaction

Figure 17. PS/2 Mouse Transaction



A PS/2-style mouse employs a relative coordinate system (see Figure ), wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving it down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a ‘1’ indicates a negative value.




mouse-uses-a-relative-coordinate-system

Figure 18. The Mouse Uses a Relative Coordinate System to Track Movement



The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeats approximately every 50 ms. The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated mouse button is being pressed.


Voltage Supply

The PS/2 port on the Universal Development Board powered by 5V. Although the Universal Development Board not a 5V-tolerant device, it can communicate with a 5V device using series current-limiting resistors, as shown in Figure 16.


Example Code

To see the demo result, click on ISE icon inside PS/2 folder of the CD.


VGA Display Port

The Universal Development Board includes a VGA display port and DB15 connector, as indicated in Figure . You can connect this port directly to most PC monitors or flat-panel LCD displays using a standard monitor cable.


As shown in Figure , the Universal Development Board controls five VGA signals: Red (R) its 1st pin in connector, Green (G) its 2nd pin, Blue (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all available on the VGA connector. The pins that drive the VGA port appear in Table . A detailed schematic is in Figure .




vga-interface-from-universal-development

Figure 19.VGA interface from Universal Development Board




Table 16. Pin connections to the VGA

Signals

PIN NAME

RED

VGA_RED

GREEN

VGA_GREEN

BLUE

VGA_BLUE

Horizontal Sync (Hs)

VGA_HS

Vertical Sync (Vs)

VGA_VS

 

 

Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Drive the R, G, and B signals High or Low to generate the eight possible colors shown in Table .


Table 17. 3-Bit Display Color Codes

 


RED

GREEN

BLUE

RESULTING COLOR

0

0

0

BLACK

0

0

1

BLUE

0

1

0

GREEN

0

1

1

CYAN

1

0

0

RED

1

0

1

MAGENTA

1

1

0

YELLOW

1

1

1

WHITE

 

 

VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 modes. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics




Signal Timing for a 60Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel by-pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and LCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure 17, information is only displayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.




vga-interface-spartan-3-primer

Figure 17. Illustration of the working of a VGA display



The size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller indicates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The board uses three bits per pixel, producing one of the eight possible colors shown in Table . The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. As shown in Figure 17, the VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal “retrace” frequency.


Example Code

To see the demo result, click on ISE icon inside VGA folder of the CD.


Push Button and Reset switch

It consist of two Push Buttons. It can be used to make an interrupt during application running. Reset switch forces the FPGA to reconfigure from the selected configuration memory source. Press and release this button to restart the FPGA configuration process at any time.




push-button-and-reset-switch-interface

Figure 21.Push Button and Reset switch Interface with >Universal Development Board



Table 18. Pin Connection with Universal Development Board

 


Signals

PIN NAME

PushButton1

PB1

PushButton2

PB2

Reset

RST

 

 
Clock Source

The Universal Development Board has a dedicated 50 MHz series clock oscillator source and an optional socket for another clock oscillator source. Figure 18 provides a detailed schematic for the clock sources.


Table 19. Clock Oscillator Sources

 


Signals

PIN NAME

50MHZ

CLK

 



clock-source-connections

Figure 18.Clock source connections from Universal Development Board



Expansion I/O Connectors

The Universal Development Board consists of 20x2 pin connector and 2 no. of 10x2 pin connectors. Figure 18 provides schematic for Expansion I/O connectors.


Table 12. Pin name for J9 and J11 10x2 pin Expansion Connector

 


Signals

10X2 EXP. CONNECTOR J9 PIN NAME

10X2 EXP. CONNECTOR J11 PIN NAME

1

CONA_1

CONA_17

2

CONA_2

CONA_18

3

CONA_3

CONA_19

4

CONA_4

CONA_20

5

CONA_5

CONA_21

6

CONA_6

CONA_22

7

CONA_7

CONA_23

8

CONA_8

CONA_24

9

CONA_9

CONA_25

10

CONA_10

CONA_26

11

CONA_11

CONA_27

12

CONA_12

CONA_28

13

CONA_13

CONA_29

14

CONA_14

CONA_30

15

CONA_15

CONA_31

16

CONA_16

CONA_32

17

VCC

VCC

18

GND

GND

19

VCC

VCC

20

GND

GND

 

 
Table 13. Pin name for J9 and J11 10x2 pin Expansion Connector

 


Signals

20X2 EXP. CONNECTOR J10 PIN NAME

Signals

20X2 EXP. CONNECTOR J10 PIN NAME

1

LCD_D0

21

VCC

2

LCD_D1

22

VCC

3

LCD_D2

23

GND

4

LCD_D3

24

GND

5

LCD_D4

25

UART_TXD0

6

LCD_D5

26

UART_RXD0

7

LCD_D6

27

UART_TXD1

8

SEGA

28

UART_RXD1

9

SEGB

29

VGA_HS

10

SEGC

30

VGA_VS

11

SEGD

31

VGA_GREEN

12

SEGE

32

VGA_BLUE

13

SEGF

33

VGA_RED

14

SEGG

34

PS2_DATA

15

SEGDP

35

PS2_CLK

16

CONA_16

36

BUZZER

17

VCC

37

ROW1

18

VCC

38

ROW2

19

GND

39

ROW3

20

GND

40

ROW4

 



expansion-i-o-connectors

Figure 19.Expansion I/O connectors in Universal Development Board



Daughter board

Spartan 3/3E FPGA Daughter board

Introduction

The purpose of this daughter board is to integrate all the necessary components for using a FPGA, but without being targeted on a special application. The board provides 141 data pins to the user, who can use them as inputs, outputs or both. The main component of the daughter board is Spartan 3 /Spartan3E FPGA, Serial PROM and JTAG Port. The following figure elaborates the denotation.




elaborates-the-denotation


Device Part Marking



device-part-marking


The second important component on this board is the XCF04S-PROM, in which you can store a bit-file. The FPGA can be programmed directly from the PROM or through the JTAG connection. If the PROM-Boot option is enabled, the FPGA will be programmed out of the PROM when the power is turned on.


Also includes a JTAG programming and debugging chain .


A general overview of the FPGA architecture is presented in the following figure.




general-overview-of-the-fpga-architecture

Figure 24. A general overview of the FPGA architecture



Configuration PROM

The Universal Development Board has an XCF04S serial configuration Flash PROM to store FPGA configuration data and potentially additional non-volatile data, including Micro Blaze application code.


Table 14. Jumper setting description: XC3S400PQG208/ XC3S500EPQG208

 


Jumper Setting

Description

JTAG

The FPGA boots from Platform Flash. No additional data storage is available

PROM

The FPGA boots from Platform Flash, which is permanently enabled. The FPGA can read additional data from Platform Flash.

NONE

Jumper removed

 

 
JTAG OPTION

For most applications, this is the default jumper setting. As shown in Figure , the Platform Flash is enabled only during configuration when the FPGA’s DONE pin is Low. When the DONE pin goes high at the end of configuration, the Platform Flash is disabled and placed in low-power mode.




   enabling-jtag
includes a 4Mbit Platform Flash configuration PROM. The XC3S400 FPGA on the board only requires slightly less than 1Mbit for configuration data. The remainder of the Platform Flash is available to store other non-volatile data, such as revision codes, serial numbers and coefficients. To allow the FPGA to read from Platform Flash after configuration, the J1 jumper must be properly positioned as shown in Figure . When the jumper is in this position, the Platform Flash is always enabled.


enabling-serial-prom

Figure 26. Enabling Serial PROM



NONE OPTION

If the J1 jumper is removed, then the Platform Flash and FPGA are disabled.


JTAG Programming/Debugging Ports

The Spartan-3 FPGA includes a JTAG programming and debugging chain. Additionally, there is JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 6-pin female header connector. The JTAG cable connects directly to the parallel port of a PC and to a standard 6-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater.


XC95288XL CPLD Daughter board

Introduction

The purpose of this daughter board is to integrate all the necessary components for using a CPLD, but without being targeted on a special application. The board provides 155 data pins to the user, who can use them as inputs, outputs or both. The main component of the daughter board is XC95288XL CPLD and JTAG Port. The following figure elaborates the denotation.

xc95288xl cpld

Device Part Marking



jtag-port


Also includes a JTAG programming and debugging chain .


JTAG Programming/Debugging Ports

The CPLD top board includes a JTAG programming and debugging chain. Additionally, there are two JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 6-pin female header connector. The JTAG cable connects directly to the parallel port of a PC and to a standard 6-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater.


A general overview of the CPLD architecture is presented in the following figure.




general-overview-of-the-cpld-architecture

Figure 25. A general overview of the CPLD architecture



ALTERA CYCLONE-3 FPGA Daughter board

Introduction

The purpose of this daughter board is to integrate all the necessary components for using EP3C16Q240C8N FPGA, but without being targeted on a special application. The board provides 150 data pins to the user, who can use them as inputs, outputs or both. The main component of the daughter board is Altera Cyclone-3 FPGA, Serial PROM and JTAG Port. The following figure elaborates the denotation.




altera-cyclone-3-fpga-serial-prom


The second important component on this board is the EPCS1S-PROM, in which you can store a bit-file. The FPGA can be programmed directly from the PROM or through the JTAG connection.


Also includes a JTAG programming and debugging chain .


JTAG Programming Ports

The Cyclone-3 top board includes a JTAG programming port. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 2x5-pin female header. The JTAG cable connects directly to the parallel port of a PC and to a standard 2x5-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater




jtag-voltage


AS Ports

The Cyclone-3 top board also includes a AS port for programming serial PROM. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the AS header. DB-25 parallel port connector connects to the 2x5-pin female header. The JTAG cable connects directly to the parallel port of a PC and to a standard 2x5-pin AS port.




jtag-cable-connects


A general overview of the FPGA architecture is presented in the following figure.




overview-of-the-cyclone-3-fpga-architecture

Figure 26. A general overview of the Cyclone-3 FPGA architecture



SPARTAN 6 FPGA DAUGHTER BOARD

Introduction

The purpose of this daughter board is to integrate all the necessary components for using a FPGA, but without being targeted on a special application. The board provides 200 data pins to the user, who can use them as inputs, outputs or both. The main component of the daughter board is Spartan 6 FPGA, JTAG Port. The following figure elaborates the denotation.




xc6slx100t-2fgg676c
Device Part Marking


xilinx-spartan-6-xc6slx16

DDR Memory

Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. DDR SDRAM, also called DDR1 SDRAM, has been superseded by DDR2 SDRAM and DDR3 SDRAM.Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a SDR SDRAM running at the same clock frequency, due to this double pumping. With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s. The DDR2 memory of Spartan 6 board can be used as store the additional data.


Jumper setting

Place the jumper at J8 to enable or disable the power supply of DDR2 memory.


Place the jumper between 1&2 for enable.


Place the jumper between 2&3 for disable.


Clock source

To perform the operation on Spartan 6 which needs clock frequency. It can be generated by oscillator.The range of frequency is 100Mhz.


JTAG Programming/Debugging Ports

The Spartan-3 FPGA includes a JTAG programming and debugging chain. Additionally, there is JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 6-pin female header connector. The JTAG cable connects directly to the parallel port of a PC and to a standard 6-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater.


VIRTEX 5 FPGA DAUGHTER BOARD

Introduction

The purpose of this daughter board is to integrate all the necessary components for using a FPGA, but without being targeted on a special application. The board provides 220 data pins to the user, who can use them as inputs, outputs or both. The main component of the daughter board is Virtex 5 FPGA, SPI flash and JTAG Port. The following figure elaborates the denotation.




virtex-5-xc5vl110-1ffg67c


Device Part Marking



virtex-5-xc5vlx50t


DDR Memory

Double data rate synchronous dynamic random-access memory (DDR SDRAM) is a class of memory integrated circuits used in computers. DDR SDRAM, also called DDR1 SDRAM, has been superseded by DDR2 SDRAM and DDR3 SDRAM.Compared to single data rate (SDR) SDRAM, the DDR SDRAM interface makes higher transfer rates possible by more strict control of the timing of the electrical data and clock signals. Implementations often have to use schemes such as phase-locked loops and self-calibration to reach the required timing accuracy. The interface uses double pumping (transferring data on both the rising and falling edges of the clock signal) to lower the clock frequency. One advantage of keeping the clock frequency down is that it reduces the signal integrity requirements on the circuit board connecting the memory to the controller. The name "double data rate" refers to the fact that a DDR SDRAM with a certain clock frequency achieves nearly twice the bandwidth of a SDR SDRAM running at the same clock frequency, due to this double pumping. With data being transferred 64 bits at a time, DDR SDRAM gives a transfer rate of (memory bus clock rate) × 2 (for dual rate) × 64 (number of bits transferred) / 8 (number of bits/byte). Thus, with a bus frequency of 100 MHz, DDR SDRAM gives a maximum transfer rate of 1600 MB/s. The DDR2 memory of Virtex 4 board can be used as store the additional data.


Jumper setting

Place the jumper at J5 to enable or disable the power supply of DDR2 memory.


Place the jumper between 1&2 for enable.


Place the jumper between 2&3 for disable.


Clock source

To perform the operation on Virtex 4 which needs clock frequency. It can be generated by oscillator.The range of frequency is 100Mhz.


USB/JTAG Programming/Debugging Ports

The Virtex 4 FPGA Board includes a USB/ JTAG programming and debugging chain. Additionally, there are two possible way for programming download and debugging through USB as well as JTAG header. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 6-pin female header connector. The JTAG cable connects directly to the parallel port of a PC and to a standard 6-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater. And another way is a mini USB cable, which is used to download the program from PC into FPGA. For this purpose the cable directly connected to USB port of the PC.


Appendix