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CoolRunner- II CPLD Kit

Introduction

Xilinx's Cool runner II, Tyro is proposed to smooth the progress of developing and debugging of various designs encompassing of Cool runner II CPLD family.

Package Contents

Xilinx CoolRunner-II CPLD Kit

☞Serial Port Cable (DTE)

☞JTAG Download Cable

☞Printed User Manual

☞5V Power AC Adaptor

☞LCD module

☞CD contains

☞Software

☞Example Programs

☞User Manual

☞Simple Projects

Learning Xilinx CPLD and ISE Development Software Basics

The CoolRunner- II Board is more advanced and simple compared to other development boards. To learn the basics of Xilinx CPLD design and how to use the Xilinx ISE development software, consider using the Starter Kit Bundle, which contains CoolRunner- II CPLD Kit at a very affordable price.

The Xilinx CoolRunner- II CPLD development board provides a low-cost, easy-to-use development and evaluation platform for CoolRunner-II CPLD designs

Components placement

Components placement

Figure 1. Xilinx CoolRunner Board Components placement

Block Diagram


Figure 2. Xilinx CoolRunner-II Board Block Diagram

Figure 2. Xilinx CoolRunner-II Board Block Diagram

On-board Peripherals

The CoolRunner CPLD Lab Kit comes with many interfacing options

☞2 Nos. of Seven-segment display

☞8-Nos. of Toggle switches (Digital Inputs)

☞8-Nos. of Point LED’s (Digital Outputs)

2x16 Character GLCD

☞4 Push Button

☞Relay / Stepper Motor driver circuit

☞Digital to Analog Converter

☞Two UART for serial port communication through PC

☞PS/2 keyboard Interface

☞Analog / Digital Converter

☞3-Bit VGA Interface

☞Piezo Electric Buzzer

Seven Segment Display

The CoolRunner-II Board has Two-character, seven segment LED display controlled by CPLD user-I/O pins, as shown in Figure 3. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each CPLD pin connected to the LED display is in table 1. To light an individual signal, drive the individual segment control signal high along with the associated anode control signal for the individual character. The segment control inputs, A through G and DP, drive the individual segments that comprise the character. A Low value lights the individual segment, a High turns off the segment. A Low on the A input signal, lights segment ‘a’ of the display. The anode controls for the remaining characters, AN[2:1] are all High, and these characters ignore the values presented on A through G and DP.

Figure 3. Seven-segment display connections from CoolRunner-II CPLD lab kit

Figure 3. Seven-segment display connections from CoolRunner-II CPLD lab kit

Table 1. Seven-segment display connections to the CPLD pins

Segment

CPLDPIN

A

P110

B

P112

C

P114

D

P117

E

P115

F

P111

G

P113

D P

P116

 

Table 2.Digit Enable (Anode Control) Signals (Active Low)

Anode Control

CPLDPIN

A N 0

P118

A N 1

P119

 

The LED control signals are time-multiplexed to display data on all two characters, as shown in Figure 4. P resent the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low. Through persistence of vision, the human brain perceives that all four characters appear simultaneously, similar to the way the brain perceives a TV display.

This “scanning” technique reduces the number of I/O pins required for the four characters. In case an CPLD pin were dedicated for each individual segment, then 32 pins are required to drive two 7-segment LED characters. The scanning technique reduces the required I/O down to 12 pins. The drawback to this approach is that the CPLD logic must continuously scan data out to the displays—a small price to save 20 additional I/O pins.



drive-anode-input-for-cooller-ii

Figure 4. Drive Anode Input Low to Light an Individual Character

Table 2. Display Characters and Resulting LED Segment Control Values

Character

a

b

c

d

e

f

g

1

1

0

0

1

1

1

1

2

0

0

1

0

0

1

0

3

0

0

0

0

1

1

0

4

1

0

0

1

1

0

0

5

0

1

0

0

1

0

0

6

0

1

0

0

0

0

0

7

0

0

0

1

1

1

1

8

0

0

0

0

0

0

0

9

0

0

0

0

1

0

0

A

0

0

0

1

0

0

0

B

1

1

0

0

0

0

0

C

0

1

1

0

0

0

1

D

1

0

0

0

0

1

0

E

0

1

1

0

0

0

0

F

0

1

1

1

0

0

0

 

Example Code

To see the demo result, click on ISE icon inside Seven Segment folder of the CD.

Digital Inputs Toggle Switch

The CoolRunner-II CPLD lab kit has eight slide switches, indicated as in Figure 5. The switches connect to an associated CPLD pin,as shown in Table 3.A detailed schematic appears in Figure 5



Digital Inputs Toggle Switch

Figure 5. Slide switches connections from CoolRunner CPLD Lab Kit

Table 3.CPLD Connections to Slide Switches

Switch

0(SW5)

1(SW6)

2(SW7)

3(SW8)

4(SW9)

5(SW10)

6(SW11)

7(SW12)

CPLD

pin

P22

P23

P24

P25

P26

P28

P30

 

P31

 

When in the UP or ON position, a switch connects the CPLD pin to VCCO, a logic High. When DOWN or in the OFF position, the switch connects the CPLD pin to ground, a logic Low. The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry, although such circuitry could easily be added to the CPLD design programmed on the board. A 10KΩ series resistor provides nominal input protection.

Example Code

To see the demo result, click on ISE icon inside Digital Input Switch folder of the CD.

Light Emitting Diodes

Light Emitting Diodes (LEDs) are the most commonly used components, usually for displaying pin’s digital states. The CoolRunner-II CPLD has eight LEDs located above the push button switches, indicated by in Figure 6.



Light Emitting Diodes

Figure 6.Point LED interface from CoolRunner CPLD Lab Kit

Table 4.CPLD connections to the LEDs

L E D

0

1

2

3

4

5

6

7

CPLD

pin

P99

P100

P102

P103

P104

P105

P107

P108

 

The cathode of each LED connects to ground via a 220 ohm Ω resistor. To light an individual LED, drive the associated CPLD control signal High, which is the opposite polarity from lighting one of the 7-segment LEDs.

Example Code

To see the demo result, click on ISE icon inside LED folder of the CD.

2x16 LCD

The CoolRunner-II Development Board prominently features a 2-line by 16-character liquid crystal display (LCD). The CPLD controls the LCD via the 8-bit data interface shown in Figure 7-1. Although the LCD supports an 8-bit data interface, the Development board uses a 4-bit data interface to remain compatible with other Xilinx development boards and to minimize total pin count.

Voltage Compatibility

The character LCD is power by +5V. The CPLD I/O signals are powered by 3.3V. However, the CPLD’s output levels are recognized as valid Low or High logic levels by the LCD. The LCD controller accepts 5V TTL signal levels and the 3.3V LVCMOS outputs provided by the CPLD meet the 5V TTL voltage level requirements.. The character LCD drives the data lines when LCD_RW is High. Most applications treat the LCD as a write only peripheral and never read from from the display.

Table 5.LCD Connection to CoolRunner-II CPLD

Signal

CPL PIN

R/W

P106

RS

P107

E

P105

D0

P104

D1

P103

D2

P101

D3

P102

D4

P100

D5

P98

D6

P97

D7

P96

 


Figure 7. LCD connections from CoolRunner CPLD Lab Kit

Figure 7. LCD connections from CoolRunner CPLD Lab Kit

Example Code

To see the demo result, click on ISE icon inside GLCD folder of the CD.

Push Button

The CoolRunner-II Development Board has 4 momentary-contact push button switches, indicated as in Figure 9.



Figure 9.Keyboard interface from CoolRunner CPLD Lab Kit

Figure 9.Keyboard interface from CoolRunner CPLD Lab Kit

Table 7. CPLD Connections to Push Button

Switch

Sw1

Sw2

Sw3

Sw4

CPLD

pin

P77

P76

P75

P74

 

Example Code

To see the demo result, click on inside Keypad folder of the CD.

Motor / Driver Section

The ULN2803A is a high-voltage, high-current Darlington transistor array. The device consists of eight npn Darlington pairs that feature high-voltage outputs with common-cathode clamp diodes for switching inductive loads. The collector-current rating of each Darlington pair is 500 mA. The Darlington pairs may be connected in Parallel for higher current capability. ULN2803 is used as a driver for port I/O lines. It is also used with source which drives more than 50mA current.



Figure 8.Stepper motor drivers and relay interface with CoolRunner-II CPLD

Figure 8.Stepper motor drivers and relay interface with CoolRunner-II CPLD

Table 8.CPLD Connections to Motor/Driver

Switch

Sw1

Sw2

Sw3

Sw4

CPLD

pin

P77

P76

P75

P74

 

Relay Section

In CPLD Lab Kit, SPDT relays are used. Relay operates on 5V DC. The outputs of the terminals of the relay are taken out on the connecter to connect the external circuitry. The relay can be connected to the CPLD through the selected DIP Switch.

Table 9.Relay Interface with CoolRunner CPLD

Signal

CPLDPIN

L S 2

P78

 

Example Code

To see the demo result, click on ISE icon inside Stepper Motor and Relay folder of the CD.

SPI DAC

The Microchip Technology Inc. MCP492X, a 2.7 – 5.5V, low-power, low DNL, 12-Bit Digital-to- Analog Converters (DACs) with optional 2x buffered output and SPI interface, provides high- accuracy and low-noise performance for industrial applications.

Features

☞12-Bit Resolution

☞±0.2 LSB DNL (typ), ±2 LSB INL (typ)

☞Single or Dual Channel

☞SPI™ Interface with 20 MHz Clock Support

☞Simultaneous latching of the Dual DACs w/LDAC

☞Fast Settling Time of 4.5 µs

☞Selectable Unity or 2x Gain Output

☞450 kHz Multiplier Mode

Table 6.DAC Interface with CoolRunner CPLD

Signals

CPLDPIN

D A C _ C S

P44

D A C _ S C K

P45

D A C _ S D I

P46

 


Figure 91.DAC Interface with CoolRunner CPLD

Figure 91.DAC Interface with CoolRunner CPLD

Example Code

To see the demo result, click on ISE icon inside DAC folder of the CD.

RS-232 Serial Port

USART stands for Universal Synchronous Asynchronous Receiver Transmitter. CoolRunner Advanced Development Board supports both types of communication. The CPLD Kit provides an RS232 port that can be driven by the CoolRunner-II CPLD. A subset of the RS232 signals is used on the CoolRunner CPLD to implement this interface (RD and TD signals). The CPLD Kit provides both male and female connector DB-9 connector, labeled P2 and P3. This board utilizes the Maxim Instruments MAX3232 RS232 driver for driving the RD and TD signals. The user provides the RS232 UART code, which resides in the CoolRunner-II CPLD.



Figure 10.CPLD Interface with RS232

Figure 10.CPLD Interface with RS232

Table 7.RS232 signals and their pin assignments to the CoolRunner CPLD

Signals

CPLDPIN

T X D 1

P 1 1

R X D 1

P 1 0

T X D 2

P 1 2

R X D 2

P 1 3

 


Figure 11.Detailed schematic of CPLD Interface with RS232

Figure 11.Detailed schematic of CPLD Interface with RS232

Example Code

To see the demo result, click on ISE icon inside RS232 folder of the CD.

PS/2 Interface

The CoolRunner II CPLD Kit includes PS/2 mouse/keyboard port. Figure 13 shows the PS/2 connector, and Table 8 shows the signals on the connector. Only pins 1 and 5 of the connector attach to the CPLD.

Table 8. PS/2 Interface with CoolRunner CPLD

Connector Name

Signals

CPLD PIN

P S 2

D A T A

P 2

P S 2

C L K

P 3

 

Table 9.PS/2 Bus Timing

Symbol

Parameter

MIN

MAX

Tck

ClockHighorLow Time

30us

50us

Tsu

Datato Clock Setup

Time

5us

20us

Thld

Clocktodata Hold

Time

5us

20us

 




Figure 12.PS/2 Bus Timing Waveforms


Figure 13.PS/2 Interface with CoolRunner-II CPLD

Figure 13.PS/2 Interface with CoolRunner-II CPLD

Both the PC mouse and the keyboard uses the two-wire PS/2 serial bus to communicate with a host device, the Spartan-3E CPLD in this case. The PS/2 bus includes both clock and data. Both the mouse and the keyboard drive the bus with identical signal timings and both use 11-bit words that include a start, stop and odd parity bit. However, the data packets are organized differently for a mouse and keyboard. Furthermore, the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard.

The PS/2 bus timing appears in PS/2 Interface with CoolRunner CPLD

Connector Name

Signals

CPLD PIN

PS2

DATA

P2

PS2

CLK

P3

 

Table 9 and Figure 12 the clock and data signals are only driven when data transfers occur; otherwise they are held in the idle state at logic High. The timing defines signal requirements for mouse-to-host communications and bidirectional keyboard communications. As shown in Figure 13, the attached keyboard or mouse writes a bit on the data line when the clock signal is High, and the host reads the data line when the clock signal is Low.

Keyboard

The keyboard uses open-collector drivers so that either the keyboard or the host can drive the two-wire bus. If the host never sends data to the keyboard, then the host can use simple input pins. A ps/2-style keyboard uses scan-codes to communicate key press data. Nearly all keyboards in use today are ps/2 style. Each key has a single, unique scan-code that is sent whenever the corresponding key is pressed. The scan-codes for most keys appear in Figure . If the key is pressed and held, the keyboard repeatedly sends the scan-code every 100 ms or so. When a key is released, the keyboard sends an “f0” key-up code, followed by the scan code of the released key. The keyboard sends the same scan code, regardless if a key has different SHIFT and non-SHIFT characters and regardless whether the SHIFT key is pressed or not. The host determines which character is intended. Some keys, called extended keys, send an “e0” ahead of the scan-code and furthermore, they might send more than one scan code. When an extended key is released, an “e0 f0” key-up code is sent, followed by the scan code.



Figure 15.PS\2 style scan-code keyboard

Figure 15.PS\2 style scan-code keyboard

The host can also send commands and data to the keyboard. Table 104 provides a short list of some often-used commands.

Table 10.Common PS/2 Keyboard Commands

Command

Description

ED

Turnon/offNumLock,Caps Lock, and ScrollLockLEDs

EE

Echo.Uponreceivinganechocommand, the keyboard replie swith the same scancode “ E E ” .

F3

Sets cancoderepeatrate . The keyboard a cknowledge sreceip to fan “F3” by returningan “FA”, after which the host sendsasecond byte to set there peatrate.

FE

Resend. Upon receiving a resendcommand, the keyboard resend sthelast scancodesent

FF

Reset. Resets the keyboard

 

The keyboard sends commands or data to the host only when both the data and clock lines are High, the Idle state, because the host is the bus master, and the keyboard checks whether the host is sending data before driving the bus. The clock line can be used as a clear to send signal. If the host pulls the clock line Low, the keyboard must not send any data until the clock is released. The keyboard sends data to the host in 11-bit words that contain a ‘0’ start bit, followed by eight bits of scan code (LSB first), followed by an odd parity bit and terminated with a ‘1’ stop bit. When the keyboard sends data, it generates 11 clock transitions at around 20 to 30 kHz, and data is valid on the falling edge of the clock as shown in Figure 124.

Mouse

A mouse generates a clock and data signal when moved; otherwise, these signals remain High, indicating the idle state. Each time the mouse is moved, the mouse sends three 11-bit words to the host. Each of the 11-bit words contains a ‘0’ start bit, followed by 8 data bits (LSB first), followed by an odd parity bit, and terminated with a ‘1’ stop bit. Each data transmission contains 33 total bits, where bits 0, 11, and 22 are ‘0’ start bits, and bits 10, 21, and 32 are ‘1’ stop bits. The three 8-bit data fields contain movement data as shown in Figure 14. Data is valid at the falling edge of the clock, and the clock period is 20 to 30 kHz.


Figure 14.PS/2 Mouse Transaction

Figure 14.PS/2 Mouse Transaction

A PS/2-style mouse employs a relative coordinate system (see Figure ), wherein moving the mouse to the right generates a positive value in the X field, and moving to the left generates a negative value. Likewise, moving the mouse up generates a positive value in the Y field, and moving it down represents a negative value. The XS and YS bits in the status byte define the sign of each value, where a ‘1’ indicates a negative value.



Figure 17.The Mouse Uses a Relative Coordinate System to Track Movement

Figure 17.The Mouse Uses a Relative Coordinate System to Track Movement

The magnitude of the X and Y values represent the rate of mouse movement. The larger the value, the faster the mouse is moving. The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value, an overflow condition. A ‘1’ indicates when an overflow occurs. If the mouse moves continuously, the 33-bit transmissions repeats approximately every 50 ms. The L and R fields in the status byte indicate Left and Right button presses. A ‘1’ indicates that the associated mouse button is being pressed.

Voltage Supply

The PS/2 port on the CoolRunner-II CPLD is powered by 5V. Although the CoolRunner-II CPLD is not a 5V-tolerant device, it can communicate with a 5V device using series current- limiting resistors, as shown in Figure 13.

Example Code

To see the demo result, click on ISE icon inside PS/2 folder of the CD.

Analog / Digital Convertor

These ADCs are SPI Bus based which is a serial bus. So the number of pins in IC is very low. Total of 4 lines are required to interface it with FPGA.

☞MISO (Master In Slave Out)

☞MOSI (Master Out Slave In)

☞SCK (Serial Clock)

☞CS (Chip Select)



.A/D Interface with CoolRunner CPLD

Figure 18.A/D Interface with CoolRunner CPLD

Table 11.A/D Interface with CoolRunner CPLD

Signals

CPLD PIN

CS

P40

SCK

P41

SO

P42

SI

P43

 

Example Code

To see the demo result, click on ISE icon inside ADC folder of the CD.

VGA Display Port

The CoolRunner II CPLD Lab Kit includes a VGA display port and DB15 connector, as indicated in Figure . You can connect this port directly to most PC monitors or flat-panel GLCD displays using a standard monitor cable.



VGA interface from CoolRunner II Board

Figure 19.VGA interface from CoolRunner II Board

As shown in Figure , the CoolRunner II CPLD controls five VGA signals: Red (R) its 1st pin in connector, Green (G) its 2nd pin, Blue (B) its 3rd pin, Horizontal Sync (HS) 13th pin, and Vertical Sync (VS) its 14th pin, all available on the VGA connector. The CPLD pins that drive the VGA port appear in Table . A detailed schematic is in Figure .

Table 16.CPLD connections to the VGA

Signals

CPLD PIN

RED

P9

GREEN

P7

BLUE

P6

HorizontalSync(Hs)

P4

VerticalSync(Vs)

P5

 

Each color line has a series resistor to provide 3-bit color, with one bit each for Red, Green, and Blue. The series resistor uses the 75 ohm VGA cable termination to ensure that the color signals remain in the VGA-specified 0V to 0.7V range. The HS and VS signals are TTL level. Drive the R, G, and B signals High or Low to generate the eight possible colors shown in Table .

Table 17.3-Bit Display Color Codes

RED

GREEN

BLUE

RESULTING COLOR

0

0

0

BLACK

0

0

1

BLUE

0

1

0

GREEN

0

1

1

CYAN

1

0

0

RED

1

0

1

MAGENTA

1

1

0

YELLOW

 

1

1

WHITE

 

VGA signal timing is specified, published, copyrighted, and sold by the Video Electronics Standards Association (VESA). The following VGA system and timing information is provided as an example of how the CPLD might drive VGA monitor in 640 by 480 modes. For more precise information or for information on higher VGA frequencies, refer to documents available on the VESA website or other electronics

☞Websites: Video Electronics Standards Association http://www.vesa.org

☞VGA Timing Information http://www.epanorama.net/documents/pc/vga_timing.html

Signal Timing for a 60Hz, 640x480 VGA Display

CRT-based VGA displays use amplitude-modulated, moving electron beams (or cathode rays) to display information on a phosphor-coated screen. GLCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel by-pixel basis. Although the following description is limited to CRT displays, GLCD displays have evolved to use the same signal timings as CRT displays. Consequently, the following discussion pertains to both CRTs and GLCD displays. Within a CRT display, current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a “raster” pattern, horizontally from left to right and vertically from top to bottom. As shown in Figure , information is only displayed when the beam is moving in the “forward” direction—left to right and top to bottom—and not during the time the beam returns back to the left or top edge of the display. Much of the potential display time is therefore lost in “blanking” periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass.



Signal Timing for a 60Hz, 640x480 VGA Display

Figure 20.Illustration of the working of a VGA display

The size of the beams, the frequency at which the beam traces across the display, and the frequency at which the electron beam is modulated determine the display resolution. Modern VGA displays support multiple display resolutions, and the VGA controller indicates the resolution by producing timing signals to control the raster patterns. The controller produces TTL-level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time. Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location. The CoolRunner-II Board uses three bits per pixel, producing one of the eight possible colors shown in Table 17.

The controller indexes into the video data buffer as the beams move across the display. The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel. As shown in Figure , the VGA controller generates the HS (horizontal sync) and VS (vertical sync) timings signals and coordinates the delivery of video data on each pixel clock. The pixel clock defines the time available to display one pixel of information. The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam intensity, with practical refresh frequencies in the 60 Hz to 120 Hz range. The number of horizontal lines displayed at a given refresh frequency defines the horizontal “retrace” frequency.

Example Code

To see the demo result, click on ISE icon inside VGA folder of the CD.

JTAG Programming/Debugging Ports

The CoolRunner II CPLD Lab Kit includes a JTAG programming and debugging chain. Additionally, there are two JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables. A PANTECH JTAG3 low-cost parallel to JTAG cable is included as part of the kit and connects to the JTAG header. DB-25 parallel port connector connects to the 6-pin female header connector. The JTAG cable connects directly to the parallel port of a PC and to a standard 6-pin JTAG programming header in the kit that can program a devices that have a JTAG voltage of 1.8v or greater.



JTAG Programming/Debugging Ports

Figure 15.JTAG connection with CoolRunner-II CPLD

This JTAG header consists of 0.1-inch stake pins, located toward the top edge of the board, directly below the two expansion connectors. The Pantech low-cost parallel port to JTAG cable fits directly over the header stake pins, as shown in Figure 15.

When properly fitted, the cable is perpendicular to the board. You must make sure that the signals at the end of the JTAG cable align with the labels listed on the board. The other end of the Pantech cable connects to the PC’s parallel port. The Pantech cable is directly compatible with the Xilinx impact software.

Clock Source

The CoolRunner CPLD Lab Kit has a dedicated 50 MHz series clock oscillator source and an optional socket for another clock oscillator source.

Table 12. Clock Oscillator Sources

Signals

CPLDPIN

SMD-50MHZ

P32

EXTCLOCK

P38

 

Appendix

Appendix I