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UART Communication with CPLD Development Kit

UART Communication with CPLD Development Kit

 

UART Stands for Universal Asynchronous Transmitter Receiver. The function of UART is conversion parallel data (8 bit) to serial data. UART transmit bytes of data sequentially one bit at a time from source and receive the byte of data at the destination by decoding sequential data with control bits. As the entire processes require no clock input from source hence it is termed as asynchronous communication.      

 

Baud Rate

In the UART communication data transmission speed is measured by Baud Rate. Baud rate describes the total number of bit sent through serial communication. It includes Start bit, Data byte, Parity bit and Stop bit. Transmitter and receiver need to be maintained in the baud rate. For example CPLD Development Kit transmit data at the baud rate of 9600 and at the receiving end PC need to be set with same baud rate using HyperTerminal or TeraTerminal.

 

Packet of Data in Serial Communication

Start

Data 0

Data 1

Data 2

Data 3

Data 4

Data 5

Data 6

Data 7

Parity

Stop

 

Serial Communication consist of 2 lines Transmitter and Receiver pin.

 

 

Fig 1:ConnectioPacket of Data in Serial Communicationn between CPLD and PC

 

Serial data communicate on CPLD side range in 0 to 3.3v.  Logic 0 is represented by 0v.

Logic 1 is represented by 3.3v

Packet of Data in Serial Communication

                                                  Fig 2: Voltage level of CPLD

 

On PC Side RS232 Port voltage range from -15v to +15v. Logic 0 is represented by +3v to 15v.

Logic 1 is represented by -3v to -15v

 Packet of Data in Serial Communication

 

                                                                Fig 3: Voltage level of PC

 

 

In order to communicate between CPLD and PC with different voltage level, MAX3232 Driver IC is required. It consists of 2 channel transmitter and Receiver.

 

Serial communication

 

The data communication of UART is made by 11 bit blocks.

Serial communication

                                                      Fig 4: Serial communication

 

The wave form showed the protocol of the UART. Here the ‘0’ bit represent as start bit which is initiated the serial communication. The start bit must be ‘0’. The next 8 bit’s are data bit. The LSB bit of data goes as first bit continue it sent other 7 bits. The 10th bit is a parity bit which is used to identify error in the communication. The parity bit is either 0 or 1 which is depending on the number of 1’s present in transmission. If even parity is used, the number of bit must be even. If odd parity is used, the number of bit must be odd. The speed of transmission is fixed which is measured by baud rate. The last bit is stop bit which must be ‘1’.

Note: The parity bit is not necessary which is optional.

 

Transmission delay

 

The transmission rate is measured by bits per second. Each bit has a fixed time duration while transmission. The transmission delay for each bit 104.16 μs which is constant till the end of communication. 

Example

The baud rate is 9600.

Transmission delay =1/9600 =104.16 μs.

 

RS 232 connector and cable

 

RS 232 connector is used to establish connection between CPLD Development Kit and PC. It is either male or female connector. Here we use only female to female connector. RS 232 connector has only 9 pins, even though the only 3 pins are enough to make a transmission between PC and CPLD such as RD,TD and GND.      

                                                                 RS232 connector                                                    

 

                                                             Fig 5:RS232 connector

 

      Table 1:

 

     Pin

                     Signal

      1

Data carrier detect(DCD)

      2

Received data(RD)

      3

Transmitted data(TD)

      4

Data terminal ready(DTR)

      5

Signal ground(GND)

      6

Data set ready(DSR)

      7

Request to send(RS)

      8

Clear to send(CS)

      9

Ring indicator(RI)

 

 

RS232 interface using Max3232 Driver IC with CPLD Development Kit

 RS232 interface using Max3232 Driver IC with CPLD Development Kit

 

                                              Fig 6: Schematic diagram of CPLD and MAX 3232

 UART Placement in CPLD Development Kit

 

UART Placement in CPLD Development Kit

 

VHDL Code describes Controlling On/Off CPLD Development Kit interfaced devices such as Relay, Buzzer, LED etc from PC HyperTerminal.

 

               This Code consists of Clock input and Receive input to Virtex5an CPLD Project Kit and 2 LED output. Clock running at 50MHz. The VHDL Code for UART receives data from PC and ON/OFF LED’s in the CPLD.

 VHDL Code describes Controlling On/Off CPLD Development Kit interfaced devices such as Relay, Buzzer, LED etc from PC HyperTerminal

 

 

 

 VHDL Code for Controlling LED’s interfaced CPLD Development Kit from PC HyperTerminal

 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity uart_reciever is

port (       clk   : in std_logic;

             din   : in  std_logic;

             led1     : out std_logic;

             led2     : out std_logic);

                                                                 

end uart_reciever;

 

architecture Behavioral of uart_reciever is

type state is (ready,b0);

signal ps : state := ready;

type state1 is (st1,st2);

signal ps1 : state1 := st1;

signal start,stop : std_logic;

signal store : std_logic_vector(7 downto 0) := "10101010";

begin

process(clk)

variable i : integer := 0 ;

begin

if clk'event and clk = '1' then

if ps = ready then

start <= din;

end if;

if start = '0' then

ps <= b0;

elsif start = '1' then

ps <= ready;

end if;

------------------------------------------1

if ps = b0 then

i := i + 1;

if i = 2600 then

start <= din;

end if;

if i = 7800 then

store(0) <= din;

end if;

if i = 13000 then

store(1) <= din;

end if;

if i = 18200 then

store(2) <= din;

end if;

if i = 23400 then

store(3) <= din;

end if;

if i = 28600 then

store(4) <= din;

end if;

if i = 33800 then

store(5) <= din;

end if;

if i = 39000 then

store(6) <= din;

end if;

if i = 44200 then

store(7) <= din;

end if;

if i = 49400 then

stop <= din;

end if;

if i = 54600 then

i := 0 ;

ps <= ready ;

-----------------------------------------------------10

end if;

end if;

end if;

end  process;

 

process(clk,store)

begin

if clk'event and clk = '1' then

if ps1 = st1 then

if store = x"31" then

led1 <= '1' ;

ps1 <= st2 ;

elsif store = x"32" then

led1 <= '0' ;

ps1 <= st2 ;

else

ps1 <= st2 ;

null;

end if;

end if;

if ps1 = st2 then

if store = x"33" then

led2 <= '1' ;

ps1 <= st1 ;

elsif store = x"34" then

led2 <= '0' ;

ps1 <= st1 ;

else

ps1 <= st1 ;

null;

end if;

end if;

end if;

end process;

 

end Behavioral;

 

 

User Constraint File

 

 

NET "clk"  LOC = "p3"  ;

NET "din"  LOC = "p33"  ;

NET "l1"  LOC = "p35"  ;

NET "l2"  LOC = "p36"  ;