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SRAM interface with Spartan3 FPGA Image Processing Board

SRAM interface with Spartan3 FPGA Image Processing Board

SRAM

Static random-access memory (SRAM) is a type of semiconductor memory that uses bistable latching circuitry to store each bit. SRAM is volatile in that data is eventually lost when the memory is not powered.

The ISSI IS61LV25616AL is a high-speed, 4,194,304-bit static RAM organized as 262,144 words by 16 bits. It is fabricated using ISSI's high-performance CMOS technology.

This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE.

The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) access.

SRAM-Cell operation

Each bit in an SRAM is stored on four transistors that form two cross-coupled inverters. This storage cell has two stable states, which are used to denote 0 and 1. Two additional access transistors serve to control the access to a storage cell during read and write operations. A typical SRAM uses six MOSFETs to store each memory bit

Interfacing SRAM with Spartan3 FPGA Image Processing BoardInterfacing SRAM with Spartan3 FPGA Image Processing Board

 The Spartan-3 EDK FPGA has a megabyte of fast asynchronous SRAM, surface mounted to the front side of the board. The memory array includes two 256Kx16 ISSI IS61LV25616AL-10T 10 ns SRAM devices, as shown in Figure. A detailed schematic appears in Figure.

The SRAM array forms either a single 256Kx32 SRAM memory or two independent 256Kx16 arrays. Both SRAM devices share common write-enable (WE#), output-enable (OE#), and address (A[17:0]) signals. However, each device has a separate chip select enable (CE#) control and individual byte-enable controls to select the high or low byte in the 16-bit data word, UB and LB, respectively.

 The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions. However, it alternately provides high-density data storage for a variety of applications, such as digital signal processing (DSP), large data FIFOs, and graphics buffers.

Schematics to Interface SRAM with Spartan3 FPGA Image Processing Board                                                     

Schematics to Interface SRAM with Spartan3 FPGA Image Processing Board                                                                                     

Schematics to Interface SRAM with Spartan3 FPGA Image Processing Board         

 SRAM Placement in Spartan3 FPGA Image Processing Board

Functional Block Diagram of SRAM

               

Functional Block Diagram of SRAM

 

Pin Descriptions of SRAM IC

A0-A17

Address Inputs

I/O0-I/O15

Data Inputs/Outputs

CE

Chip Enable Input

OE

Output Enable Input

WE

Write Enable Input

LB

Lower-byte Control (I/O0-I/O7)

UB

Upper-byte Control (I/O8-I/O15)

Vdd

Power

GND

Ground

SRAM Address Bus Connection with FPGA

A17

   P23


 
SRAM Write Enable and Output Enable Control Signals

Signals

FPGA Pins

OE#

   P24

WE#

   P25


 
SRAM Data Signals, Chip Enables, and Byte Enables

Signals

FPGA Pins

D0

   P27

D1

   P28

D2

   P30

D3

   P31

D4

   P32

D5

   P33

D6

   P35

D7

   P36

D8

   P41

D9

   P44

D10

   P46

D11

   P47

D12

   P50

D13

   P51

D14

   P52

D15

   P53

CE1

   P56

CE2

   P137

UB1

   P57

LB1

   P59

UB2

   P140

LB2

   P141