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Slide switch and Push Button interfacing with Spartan3e FPGA Development Kit

Slide switch and Push Button interfacing with Spartan3e FPGA Development Kit

 Slide switch

 Slide switches are most common used in electronic circuits for digital input of ON/OFF states. They allow control over current flow in a circuit. You’ll usually find slide switches in SPDT or DPDT configurations.

 Push Buttons

 Push-button switches are the classic momentary switch. Typically these switches have a really nice, tactile feedback when you press them.  

Schematic to interface Slide Switch and Push Button with Spartan3e FPGA Development Kit

Schematic to interface Slide Switch and Push Button with Spartan3e FPGA Development Kit

 

Slide Switch and Push Button Placement in Spartan3e FPGA Development Kit

Slide Switch and Push Button Placement in Spartan3e FPGA Development Kit

 Interfacing Slide Switch and Push Button with Spartan3e FPGA Development Kit

Push Button interface is straight forward. One end of Push Button connected to FPGA and another end connected to ground. Slide switch interface to FPGA is Pulled High by default at open end and another end is connected to ground which act as OFF State.

VHDL Code for Slide Switch Interfacing with Spartan3e FPGA Development Kit

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity sw_led is

    Port ( sw : in  STD_LOGIC_VECTOR (15 downto 0);

           led : out  STD_LOGIC_VECTOR (15 downto 0));

end sw_led;

 

architecture Behavioral of sw_led is

 

begin

led<=sw;

 

end Behavioral;

User Constraint File

pre class="brush: js;"> NET "led[0]" LOC = P41;

NET "led[1]" LOC = P42;

NET "led[2]" LOC = P45;

NET "led[3]" LOC = P47;

NET "led[4]" LOC = P48;

NET "led[5]" LOC = P49;

NET "led[6]" LOC = P50;

NET "led[7]" LOC = P55;

NET "led[8]" LOC = P60;

NET "led[9]" LOC = P61;

NET "led[10]" LOC = P62;

NET "led[11]" LOC = P63;

NET "led[12]" LOC = P64;

NET "led[13]" LOC = P65;

NET "led[14]" LOC = P68;

NET "led[15]" LOC = P69;

NET "sw[0]" LOC = P6;

NET "sw[1]" LOC = P14;

NET "sw[2]" LOC = P20;

NET "sw[3]" LOC = P26;

NET "sw[4]" LOC = P32;

NET "sw[5]" LOC = P43;

NET "sw[6]" LOC = P51;

NET "sw[7]" LOC = P54;

NET "sw[8]" LOC = P57;

NET "sw[9]" LOC = P58;

NET "sw[10]" LOC = P71;

NET "sw[11]" LOC = P72;

NET "sw[12]" LOC = P80;

NET "sw[13]" LOC = P91;

NET "sw[14]" LOC = P101;

NET "sw[15]" LOC = P110;

VHDL Code for Push Button Interfacing with Spartan3e FPGA Development Kit

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

 

entity push_lcd is

port(clock:in std_logic;    ----clock i/p

     rw: out std_logic;     ---read write control

     rs:out std_logic;      ----command data control

     en:out std_logic;  

        a2 :in std_logic_vector(1 downto 0) ;

         ----lcd enable

        ---_vector(3 downto 0) ;     ---row scan line

        ---column scan line

     data:out std_logic_vector(7 downto 0));   -----data lines

end push_lcd;

 

architecture arch of push_lcd is 

type state is(state1,state2,state6);    ---fsm for data

signal ro : state := state1;

signal a1 : std_logic_vector(1 downto 0);

signal z :std_logic_vector(1 downto 0);

 

begin 

process(clock)

variable output : std_logic_vector(1 downto 0) := "11" ;  ----logic high connection

variable input : std_logic_vector(1 downto 0) := "00" ;   ----logic low connection

variable verify : std_logic_vector(1 downto 0) ;

variable verify1 : std_logic_vector(1 downto 0)  ; 

variable i,j : integer := 0 ;

variable datas,datam : std_logic_vector(7 downto 0) := "00110001";

begin 

rw<='0';

-------------------------------------------------------------------------

if clock'event and clock='1' then

if ro = state1 then

z <= input ;

else

z <= (OTHERS => 'Z');

end if;

if ro /= state1 then

a1 <= output ;

else

a1 <= (OTHERS => 'Z');

end if;

verify1 := a1 ;

verify := a2 ;

case ro is

when state1 =>       -----column scan state

case verify1 is

when "01" =>     ---no key pressed

ro <= state1 ;

when "00" =>   ---1st column

datas  := x"31";

ro <= state2;

when others =>

ro <= state1 ;

end case;

 

when state2 =>   ----1st row scan logic

case verify is

when "10" =>

datam := x"31";

ro <= state6 ;

when "01" =>

datam := x"32";

ro <= state6;

when others =>

ro <= state2 ;

end case;

 

when state6 =>

if i <= 500000 then

i := i + 1;

elsif i > 500000 then

i := 0 ;

if j < 36 then

j := j + 1 ;

ro <= state6;

elsif j = 36 then

j := 0 ;

ro <= state1;

end if;

end if;

case j is

when 1=>

data<="00111000";     ---ascii code of data to be displayed

en<='1';

rs<='0';  

when 2=>

data<="00111000";

rs<='0';

en<='0';  

when 3=>

data<="00001110";

en<='1';

rs<='0'; 

when 4=>

data<="00001110";

rs<='0'; 

en<='0'; 

when 5=>

data<="00000001";

en<='1';

rs<='0';  

when 6=>

data<="00000001";

rs<='0'; 

en<='0'; 

when 7=>

data<="00000110";

en<='1';

rs<='0';  

when 8=>

data<="00000110";

rs<='0'; 

en<='0'; 

when 9=>

data<="10000000";

en<='1';

rs<='0';  

when 10=>

data<="10000000";

rs<='0'; 

en<='0'; 

--------------------------------------------------------------------------------

when 11=>

data<="01010010";    --  ascii code for "R"

en<='1';

rs<='1';  

when 12=>

data<="01010010";    --  ascii code for "R"

rs<='1'; 

en<='0'; 

when 13=>

data<="01001111";    --  ascii code for "O"

en<='1';

rs<='1';  

when 14=>

data<="01001111";   --   --  ascii code for "O"

rs<='1'; 

en<='0'; 

when 15=>

data<=  "01010111";         --  ascii code for "W"

en<='1';

rs<='1';  

when 16=>

data<= "01010111";          --  ascii code for "W"

rs<='1'; 

en<='0'; 

when 17=>

data<="00100000";         --  ascii code for "SPACE"

en<='1';

rs<='1'; 

when 18=>

data<="00100000";          --  ascii code for "SPACE"

rs<='1'; 

en<='0'; 

when 19=>

data<="00111010";         --  ascii code for ":"

en<='1';

rs<='1';  

when 20=>

data<="00111010";          --  ascii code for ":"

rs<='1'; 

en<='0'; 

----------------------------------------------------------------

when 21=>

data<=datam;          --  ascii code for " "

rs<='1'; 

en<='1';

when 22=>

data<=datam;          --  ascii code for " "

rs<='1'; 

en<='0';

when 23=>

data<="00100000";          --  ascii code for "SPACE"

rs<='1'; 

en<='1';

when 24=>

data<="00100000";          --  ascii code for "SPACE"

rs<='1'; 

en<='0';

when 25=>

data<="01000011";          --  ascii code for "C"

rs<='1'; 

en<='1';

when 26=>

data<="01000011";          --  ascii code for "C"

rs<='1'; 

en<='0';

-----------------------------------------------------------------

when 27=>

data<="01001111";          --  ascii code for "O"

rs<='1'; 

en<='1';

when 28=>

data<="01001111";          --  ascii code for "O"

rs<='1'; 

en<='0';

when 29=>

data<="01001100";          --  ascii code for "L"

en<='1';

rs<='1'; 

when 30=>

data<="01001100";          --  ascii code for "L"

rs<='1'; 

en<='0';

when 31=>

data<="00100000";          --  ascii code for "SPACE"

rs<='1'; 

en<='1';

when 32=>

data<="00100000";          --  ascii code for "SPACE"

rs<='1'; 

en<='0';

when 33=>

data<="00111010";          --  ascii code for ":"

rs<='1'; 

en<='1';

when 34=>

data<="00111010";          --  ascii code for ":"

rs<='1'; 

en<='0';

when 35=>

data<=datas;          --  ascii code for " "

rs<='1'; 

en<='1';

when 36=>

data<=datas;          --  ascii code for " "

rs<='1'; 

en<='0';

-----------------------------------------------------------------

when others=>

data<=datas;          --  ascii code for " "

rs<='1'; 

en<='0';

end case;

end case;

----------------------------------------------

end if;

----------------------------------------------

end process;

end arch;

User Constraint File

 

NET "data[0]" LOC = P163;

NET "data[1]" LOC = P162;

NET "data[2]" LOC = P161;

NET "data[3]" LOC = P160;

NET "data[4]" LOC = P153;

NET "data[5]" LOC = P152;

NET "data[6]" LOC = P151;

NET "data[7]" LOC = P150;

NET "a2[0]" LOC = P184;

NET "a2[1]" LOC = P183;

NET "clock" LOC = P185;

NET "en" LOC = P164;

NET "rs" LOC = P167;

NET "rw" LOC = P165;