You have no items in your shopping cart.

Subtotal: 0.00

Slide switch

Slide switches are most common used in electronic circuits for digital input of ON/OFF states. They allow control over current flow in a circuit. You’ll usually find slide switches in SPDT or DPDT configurations.

Push Buttons

Push-button switches are the classic momentary switch. Typically these switches have a really nice, tactile feedback when you press them.

Schematic to interface Slide Switch and Push Button with Spartan3 FPGA Development Kit

Schematic to interface Slide Switch and Push Button with Spartan3 FPGA Development Kit

Slide Switch and Push Button Placement in Spartan3 FPGA Development Kit

Slide Switch and Push Button Placement in Spartan3 FPGA Development Kit

Interfacing Slide Switch and Push Button with Spartan3 FPGA Development Kit

Interfacing Slide Switch and Push Button with Spartan3 FPGA Development Kit

Push Button interface is straight forward. One end of Push Button connected to FPGA and another end connected to ground. Slide switch interface to FPGA is Pulled High by default at open end and another end is connected to ground which act as OFF State.

VHDL Code for Slide Switch Interfacing with Spartan3 FPGA Development Kit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sw_led is
    Port ( a : in  STD_LOGIC_VECTOR (9 downto 0);
           b : out  STD_LOGIC_VECTOR (9 downto 0));
end sw_led;

architecture Behavioral of sw_led is

begin

b <= a;

end Behavioral;

User Constraint File

NET "a[0]" LOC = P18;
NET "a[1]" LOC = P19;
NET "a[2]" LOC = P20;
NET "a[3]" LOC = P21;
NET "a[4]" LOC = P24;
NET "a[5]" LOC = P25;
NET "a[6]" LOC = P27;
NET "a[7]" LOC = P28;
NET "b[0]" LOC = P7;
NET "b[1]" LOC = P8;
NET "b[2]" LOC = P10;
NET "b[3]" LOC = P11;
NET "b[4]" LOC = P12;
NET "b[5]" LOC = P13;
NET "b[6]" LOC = P15;
NET "b[7]" LOC = P16;

VHDL Code for Push Button Interfacing with Spartan3 FPGA Development Kit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity push_sw is
    Port (sw1,sw2: in  STD_LOGIC;
           led1,led2: out  STD_LOGIC);
end push_sw;

architecture Behavioral of push_sw is
begin
led2<= sw2;
led1<= sw1;
end Behavioral;

User Constraint File

NET "led1" LOC = P7;
NET "led2" LOC = P8;
NET "sw1" LOC = P29 | PULLDOWN;
NET "sw2" LOC = P30 | PULLDOWN;