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Seven Segment Display interfacing with Spartan3 XC3S200 FPGA Development Kit

Seven Segment Display is most commonly used to display Alpha Numeric character set. Each segment is capable of displaying values 0-9 and A-F. There are two types of seven segment display commonly used in FPGA development board. They are common anode display and common cathode display.

Seven

Interfacing with Spartan3 FPGA Development Kit

FPGA I/O lines can be easily connected with seven segment display.

Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each FPGA Pin connected to the LED display. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.

Schematics to interface Seven segment with Spartan3 FPGA Development Kit

Schematics to interface Seven segment with Spartan3 FPGA Development Kit

Seven Segment placement in Spartan3 FPGA Development Kit

Schematics to interface Seven segment with Spartan3 FPGA Development Kit

VHDL Code description

VHDL Code describes counting values from 0-9 in all the segments at the same time. Clock source in the FPGA run at 50 MHz i.e. 20ns. In order to achieve the clock speed at 1s clock divider is used. High value on all Selection line activates all the display. To display one in the segment “11111001” value need to be sent as shown in figure.

 

VHDL_Code_description.jpg

Flow chart for displaying 0-9 in all seven segments

Flow_chart_for_displaying_0-9_in_all_seven_segments

VHDL code for displaying 1-9 in all seven segments

library ieee;
use ieee.std_logic_1164.all; 
use ieee.std_logic_arith.all;	  
use ieee.std_logic_unsigned.all; 

entity seven_segment  is 

port(clk    : in  std_logic;     
     y      : out std_logic_vector(7 downto 0);
    sel     : out std_logic_vector(3 downto 0)
     ); 
end seven_segment;
--------------------
architecture bhv of seven_segment  is
type state is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9);
signal next_state,ps: state := state0;
begin 
sel <= "1111";
process(clk,next_state) ---
variable i : integer := 0 ;
begin
if clk'event and clk = '1' then
if i <= 50000000 then
i := i + 1;
elsif i > 50000000 then
i := 0 ;
next_state <= ps ;
end if;
if next_state = state0 then
y <= x"c0" ;
ps <= state1;
elsif next_state = state1 then
y <= x"f9";
ps <= state2;
elsif next_state = state2 then
y <= X"a4";
ps <= state3;
elsif next_state = state3 then
y <= X"b0";
ps <= state4;
elsif next_state = state4 then
y <= X"99";
ps <= state5;
elsif next_state = state5 then
y <= X"92";
ps <= state6;
elsif next_state = state6 then
y <= X"82";
ps <= state7;
elsif next_state = state7 then
y <= X"f8";
ps <= state8;
elsif next_state = state8 then
y <= X"80";
ps <= state9;
elsif next_state = state9 then
y <= X"98";
ps <= state1;
end if;
end if;
end process;
end bhv;

User Constraint File

NET "clk"  LOC = "p55"  ;
NET "sel(0)"  LOC = "p128"  ;
NET "sel(1)"  LOC = "p127"  ;
NET "sel(2)"  LOC = "p124"  ;
NET "sel(3)"  LOC = "p125"  ;
NET "y(0)"  LOC = "p129"  ;
NET "y(1)"  LOC = "p130"  ;
NET "y(2)"  LOC = "p131"  ;
NET "y(3)"  LOC = "p132"  ;
NET "y(4)"  LOC = "p135"  ;
NET "y(5)"  LOC = "p137"  ;
NET "y(6)"  LOC = "p140"  ;
NET "y(7)"  LOC = "p141"  ;