You have no items in your shopping cart.

Subtotal: 0.00

LED interfacing with Spartan3e FPGA Development Kit

LED interfacing with Spartan3e FPGA Development Kit

 It’s always interesting to glow LED’s on any piece of hardware. What you can do with those LED’s? You can Blink them, you can Scroll from Left to Right and Right to Left, you can Count them , you can display any logic output which can be ‘0’ or ‘1’.

Spartan3e FPGA Development Kit got array of 10 LED’s to perform all the above mentioned operations. We are here to explore more on how to perform binary counter with those LED’s. 

Now we are going to construct 16- bit Binary Counter. The 16-bit Synchronous Binary Counter counts sequentially on positive edge of every clock cycle. 

Schematics to interface LED with Spartan3e FPGA Development Kit

Schematics to interface LED with Spartan3e FPGA Development Kit

 

 LED Placement in Spartan3e FPGA Development Kit

LED Placement in Spartan3e FPGA Development Kit

VHDL Code for 16-Bit Binary Counter

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

 

entity counter is

port(Clock, PRE : in  std_logic;

Q : out std_logic_vector(15 downto 0));

end counter;

 

architecture bhv of counter is 

signal tmp: std_logic_vector(15 downto 0);

begin

 

process (Clock, PRE)

begin  

if (PRE='1') then  

tmp <= (others => '0'); 

elsif (Clock'event and Clock='1') then

tmp <= tmp + 1;

end if;    

end process;

Q <= tmp;

end bhv;

From the above code, we will get counter running at 50MHz Speed which means it will count at the speed of 20 ns. You can’t visibly see the output of Counter with LED’s at 20 ns. Instead you can check them in simulation. To make the count visible we are introducing 33 bit clock divider and assign the last 16 MSB bits to the output LED’s. This gives the result of binary count at every 1s.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

 

entity counter is

port(Clock, PRE : in  std_logic;

         Q : out std_logic_vector(15 downto 0));

end counter;

 

architecture arch of counter is 

signal tmp: std_logic_vector(32 downto 0);

begin

 

process (Clock, PRE)

begin  

if (PRE='1') then  

tmp <= (others => '0'); 

elsif (Clock'event and Clock='1') then

tmp <= tmp + 1;

end if;    

end process;

Q <= tmp(32 downto 17);

end arch;

Pin Assignment for Spartan3e FPGA Development Kit

NET "Q[0]" LOC = P41;

NET "Q[1]" LOC = P42;

NET "Q[2]" LOC = P45;

NET "Q[3]" LOC = P47;

NET "Q[4]" LOC = P48;

NET "Q[5]" LOC = P49;

NET "Q[6]" LOC = P50;

NET "Q[7]" LOC = P55;

NET "Q[8]" LOC = P60;

NET "Q[9]" LOC = P61;

NET "Q[10]" LOC = P62;

NET "Q[11]" LOC = P63;

NET "Q[12]" LOC = P64;

NET "Q[13]" LOC = P65;

NET "Q[14]" LOC = P68;

NET "Q[15]" LOC = P69;

 

NET "Clock" LOC = P185;

NET "PRE" LOC = P6;