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How to Interface Traffic light with FPGA/CPLD UDB

Traffic light controller

Four way Traffic light controller which Has Red, Yellow and Green LEDS to display current status.

Interfacing TLC with FPGA/CPLD

The Spartan-3 board has Traffic light controller with FPGA/CPLD I/O pins (details tabulated below). Traffic light controller card consist of 12 Nos. Point led arranged by 4Lanes. Each lane has Go (Green), Listen (Yellow) and Stop (Red) LED is being placed. Each LED has provided for current limiting resistor to limit the current flows to the LEDs.

 

Pin Assignment with FPGA/CPLD



DIRECTION

PIN NAME

NORTH

GO

GLCD_D2

LISTEN

GLCD_D3

STOP

GLCD_D4

WEST

 

GO

GLCD_D5

LISTEN

GLCD_D6

STOP

GLCD_D7

SOUTH

 

GO

GLCD_CS1

LISTEN

GLCD_CS2

STOP

GLCD_RS

EAST

GO

GLCD_RW

LISTEN

GLCD_D0

STOP

GLCD_D1

 

 

Schematics to Interface Traffic Light with FPGA/CPLD





VHDL Program for TLC using FPGA/CPLD

***************************************************************************************

Title : Program for Traffic Light Controller

***************************************************************************************

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity stepper is port( clk : in std_logic ; sw : in std_logic ; op1 : out std_logic ; op2 : out std_logic ; op3 : out std_logic ; op4 : out std_logic ; end entity stepper; architecture rtl of stepper is type state1 is (ready1,b01,b02,b03); signal ps1 : state1 := ready1; begin process(clk,sw1) variable i: integer := 0 ; begin if clk'event and clk = '1' then if sw = '1' then if ps1 = ready1 then i := i + 1; if i = 800000 then op1 <= '0' ; op2 <= '0' ; op3 <= '0' ; op4 <= '1' ; ps1 <= b01; i := 0; end if; end if; if ps1 = b01 then i := i + 1; if i = 800000 then op1 <= '0' ; op2 <= '0' ; op3 <= '1' ; op4 <= '0' ; ps1 <= b02; i := 0; end if; end if; if ps1 = b02 then i := i + 1; if i = 800000 then op1 <= '0' ; op2 <= '1' ; op3 <= '0' ; op4 <= '0' ; ps1 <= b03; i := 0; end if; end if; if ps1 = b03 then i := i + 1; if i = 800000 then op1 <= '1' ; op2 <= '0' ; op3 <= '0' ; op4 <= '0' ; ps1 <= ready1; i := 0; end if; end if; end if; end if; end process; end architecture rtl;