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How to Interface Stepper Motor with FPGA/CPLD UDB

Stepper Motor

A stepper motor (or step motor) is a brushless DC electric motor that divides a full rotation into a number of equal steps.

Interfacing Stepper Motor with FPGA/CPLD UDB

The Spartan-3 Primer board has external stepper motor interfacing, indicated as in Figure. Stepper Motor is driven by ULN2803A. It is a high-voltage, high-current Darlington transistor array. ULN2803 is used as a driver for port I/O lines, drivers output connected to stepper motor, PTB connector provided for external power supply if needed.

 

Pin Assignment with FPGA/CPLD UDB



Signals

PIN NAME

Stepper Motor Control A

STEP1

Stepper Motor Control B

STEP 2

Stepper Motor Control C

STEP 3

Stepper Motor Control D

STEP 4

 



Schematics to Interface Stepper Motor with FPGA/CPLD





VHDL Program for Stepper Motor using FPGA/CPLD

***************************************************************************************

Title : Program for Stepper Motor

***************************************************************************************

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity stepper is port( clk : in std_logic ;

sw : in std_logic ;

op1 : out std_logic ;

op2 : out std_logic ;

op3 : out std_logic ;

op4 : out std_logic ;

end entity stepper ;

architecture rtl of stepper is type state1 is (ready1,b01,b02,b03);

signal ps1 : state1 := ready1;

begin process(clk,sw1) variable i: integer := 0 ;

begin if clk'event and clk = '1' then

if sw = '1' then

if ps1 = ready1 then i := i + 1;

if i = 800000 then op1 <= '0' ;

op2 <= '0' ;

op3 <= '0' ;

op4 <= '1' ;

ps1 <= b01;

i := 0;

end if;

end if;

if ps1 = b01 then i := i + 1;

if i = 800000 then op1 <= '0' ;

op2 <= '0' ; op3 <= '1' ;

op4 <= '0' ; ps1 <= b02;

i := 0; end if; end if;

if ps1 = b02 then i := i + 1;

if i = 800000 then op1 <= '0' ;

op2 <= '1' ;

op3 <= '0' ;

op4 <= '0' ;

ps1 <= b03;

i := 0;

end if;

end if;

if ps1 = b03 then i := i + 1;

if i = 800000 then op1 <= '1' ;

op2 <= '0' ;

op3 <= '0' ;

op4 <= '0' ;

ps1 <= ready1;

i := 0;

end if;

end if;

end if;

end if;

end process;

end architecture rtl;