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How to Interface PS/2 with FPGA/CPLD UDB

PS/2

PC mouse and the keyboard use the two-wire PS/2 serial bus to communicate with a host device.

Interfacing PS/2 with FPGA/CPLD UDB

PS/2 Connector allows direct connection between FPGA and devices which use PS/2 communication, such as a PC, a keyboard or a mouse. For example, FPGA/CPLD can be connected either to a keyboard to capture pressed keys or to a PC to act as a keyboard. CLK and DATA lines are used for data transfer. They are connected to the FPGA I/O Pins.

 

Pin Assignment with FPGA/CPLD UDB



Signals

PIN NAME

DATA

PS2_DATA

CLK

PS2_CLK

 

Note: Please refer User Manual for Pin number of FPGA/CPLD .

Schematics to Interface PS/2 FPGA/CPLD UDB





VHDL Code for PS/2 using FPGA/CPLD

***************************************************************************************

Title : Program for UART to LED Display

***************************************************************************************

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity key is port( data: in std_logic; pclk: in std_logic;

l1 : out std_logic; l2 : out std_logic;

l3 : out std_logic; l4 : out std_logic;

l5 : out std_logic; l6 : out std_logic;

l7 : out std_logic; l8 : out std_logic);

end key;

architecture Behavioral of key is type state is (state1,state2,state3,state4,state5,state6,state7,state8,state9,state10,state11);

signal ps,ns : state;

signal store : std_logic_vector(7 downto 0):="00000000";

signal start,parity,stop : std_logic;

begin process(pclk,data) begin if pclk'event and pclk = '1' then ps <= ns;

end if;

if pclk'event and pclk = '0' then

if ps = state3 then store(1) <= data;

ns <= state4;

elsif ps = state4 then store(2) <= data;

ns <= state5;

elsif ps = state5 then store(3) <= data;

ns <= state6;

elsif ps = state6 then store(4) <= data;

ns <= state7;

elsif ps = state7 then store(5) <= data;

ns <= state8;

elsif ps = state8 then store(6) <= data;

ns <= state9;

elsif ps = state9 then store(7) <= data;

ns <= state10;

elsif ps = state10 then parity <= data;

ns <= state11;

elsif ps = state11 then stop <= data;

ns <= state1;

end if; end if; end process;

process(store) begin l1 <= store(0);

l2 <= store(1);

l3 <= store(2);

l4 <= store(3);

l5 <= store(4);

l6 <= store(5);

l7 <= store(6);

l8 <= store(7);

end process;

end Behavioral;