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How to Interface Buzzer with FPGA/CPLD UDB


Piezo buzzer is an electric component that comes in different shapes and sizes, which can be used to create sound waves when provided with electrical signal.

Interfacing Piezo buzzer with FPGA/CPLD UDB

The Universal Development board has Piezo buzzer, indicated as in Figure. Buzzer is driven by transistor Q. FPGA/CPLD can create sound by generating a PWM(Pulse Width Modulated) signal – a square wave signal, which is nothing more than a sequence of logic zeros and ones. Frequency of the square signal determines the pitch of the generated sound. To enable buzzer place jumper JP7 at E label mark position.


Pin Assignment with FPGA/CPLD UDB


Pin Name





Circuit Diagram to Interface Buzzer with FPGA/CPLD

VHDL Program for Buzzer using FPGA/CPLD

library IEEE;




entity buzz is port ( clock : in std_logic; a : out std_logic );

end buzz;

architecture Behavioral of buzz is begin process(clock) variable i : integer := 0;

begin if clock'event and clock = '1' then

if i <= 50000000 then i := i + 1; a <= '1';

elsif i > 50000000 and i < 100000000 then i := i + 1; a <= '0';

elsif i = 100000000 then i := 0;

end if;

end if;

end process;

end Behavioral;