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Seven Segment Display

A seven-segment display (SSD), or seven-segment indicator, is a form of electronic display device for displaying decimal numerals that is an alternative to the more complex dot-matrix displays.

Interfacing Seven-Segment with FPGA/CPLD UDB

The Universal Development Board has a six-character, seven-segment LED display controlled by FPGA/CPLD UDB user-I/O pins, as shown in Figure. Each digit shares eight common control signals to light individual LED segments. Each individual character has a separate anode control input. The pin number for each FPGA/CPLD pin connected to the LED display is shown in Table. To light an individual signal, drive the individual segment control signal Low along with the associated anode control signal for the individual character.

Pin Assignment with FPGA/CPLD UDB



Segment

PIN Name

A

SEGA

B

SEGB

C

SEGC

D

SEGD

E

SEGE

F

SEGF

G

SEGG

DP

SEGDP

AN5

DIGIT6

AN4

DIGIT5

AN3

DIGIT4

AN2

DIGIT3

AN1

DIGIT2

AN0

DIGIT1



Schematics to Interface 7-Segment with FPGA/CPLD





VHDL Code for 7-Segment using FPGA/CPLD


***************************************************************************************

Title : Program to Display in 7-Segment

***************************************************************************************

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration

if --library UNISIM; --use UNISIM.VComponents.all;

entity sevenseg is port(clk : in std_logic; y : out std_logic_vector(7 downto 0);

sel : out std_logic_vector(5 downto 0) );

end sevenseg ;

architecture beav of sevenseg is type state is (state0,state1,state2,state3,state4,state5,state6,state7,state8,state9);

signal next_state,ps: state := state0; begin sel <= "111111";

process(clk,next_state) --- variable i : integer := 0 ;

begin if clk'event and clk = '1' then

if i <= 100000000 then i := i + 1;

elsif i > 100000000 then i := 0 ;

next_state <= ps ;

end if;

if next_state = state0 then y <= x"c0" ;

ps <= state1;

elsif next_state = state1 then y <= x"f9";

ps <= state2;

elsif next_state = state2 then y <= X"a4";

ps <= state3;

elsif next_state = state3 then y <= X"b0";

ps <= state4;

elsif next_state = state4 then y <= X"99";

ps <= state5;

elsif next_state = state5 then y <= X"92";

ps <= state6;

elsif next_state = state6 then y <= X"82";

ps <= state7;

elsif next_state = state7 then y <= X"f8";

ps <= state8;

elsif next_state = state8 then y <= X"80";

ps <= state9;

elsif next_state = state9 then y <= X"98";

ps <= state1;

end if;

end if;

end process;

end beav;