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How to Interface 2x16 LCD with FPGA/CPLD UDB

2x16 LCD

A liquid crystal display (LCD) is a flat panel display that uses the light modulating properties of liquid crystals (LCs).

Interfacing 2x16 LCD with FPGA/CPLD UDB

The Universal Development Board has 2x16 LCD, indicated as in Figure. The 2x16 character LCD interface card with supports both modes 4-bit and 8-bit interface, and also facility to adjust contrast through trim pot. In 8-bit interface 11 lines needed to create 8-bit interface; 8 data bits (D0 – D7), three control lines, address bit (RS), read/write bit (R/W) and control signal (E). The LCD controller is a standard KS0070B or equivalent, which is a very well-known interface for smaller character based LCDs.

 

Pin Assignment with FPGA/CPLD UDB



Signal

PIN Name

R/W

LCD_RW

RS

LCD_RS

E

LCD_E

D0

LCD_D0

D1

LCD_D1

D2

LCD_D2

D3

LCD_D3

D4

LCD_D4

D5

LCD_D5

D6

LCD_D6

D7

LCD_D7

 

 

Note: Please refer User Manual for Pin number of FPGA/CPLD .

  • VCC -+5V display power supply
  • GND -Reference ground
  • Vo -GLCD contrast level from potentiometer P4
  • RS -Data (High), Instruction (Low) selection line
  • R/W - Determines whether display is in Read or Write mode.
  • E - Display Enable line
  • D0–D7 -Data lines
  • RST -Display reset line
  • Vee - Reference voltage for GLCD contrast potentiometer P3
  • LED+ -Connection with the backlight LED anode
  • LED- - Connection with the backlight LED cathode

Schematics to Interface 2x16 LCD with UDB





VHDL Code for 2x16 LCD using FPGA/CPLD

***************************************************************************************

Title : Program for UART to LED Display

***************************************************************************************

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating

---- any Xilinx primitives in this code. --library UNISIM;

--use UNISIM.VComponents.all;

entity lcd_disp is port ( clk : in std_logic;

----clock i/p lcd_rw : out std_logic;

---read&write control lcd_e : out std_logic;

----enable control lcd_rs : out std_logic;

----data or command control data : out std_logic_vector(7 downto 0));

---data line end lcd_disp; architecture Behavioral of lcd_disp is constant N: integer :=22;

type arr is array (1 to N) of std_logic_vector(7 downto 0);

constant datas : arr := (X"38",X"0c",X"06",X"01",X"C0",X"50",x"41",x"4e",x"54",x"45",x"43",x"48",x"20",x"53", x"4f",x"4c",x"55", x"54",x"49",x"4f",x"4e",X"53");

--command and data to display begin lcd_rw <= '0';

----lcd write process(clk) variable i : integer := 0;

variable j : integer := 1;

begin if clk'event and clk = '1' then

if i <= 1000000 then i := i + 1;

lcd_e <= '1';

data <= datas(j)(7 downto 0);

elsif i > 1000000 and i < 2000000 then i := i + 1;

lcd_e <= '0';

elsif i = 2000000 then j := j + 1; i := 0;

end if;

if j <= 5 then lcd_rs <= '0';

---command signal elsif j > 5 then lcd_rs <= '1';

----data signal end if;

if j = 22 then ---repeated display of data j := 5;

end if;

end if;

end process;

end Behavioral;