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16x2 LCD Interface with Spartan6 FPGA Project Kit

16x2 LCD interfacing with Spartan 6 FPGA project Board

 LCD

The expansion of LCD is Liquid Crystal Display which is used to display the character. The character is represented as the ASCII value (American Standard Code for Information Interchange). To display the character only the ASCII values are sent to LCD. The ASCII is 8bit. Here we have used 16x2 LCD with 5x8 pixel matrix (per character). The definition of 16x2 is the LCD contains 2 rows and 16 characters can be displayed per line. The single character displayed in 5x8 pixel matrix.                     LCD display                                                     

Fig 1: LCD display

 Pin details

Pin no

      Name

              Function

    Description

     1

       Vss

         Power supply

      Ground

     2

       Vdd

         Power supply

         +5v

     3

        Vo

        Contrast adjust

         0-5v

     4

        RS

           Command     

  Register select

     5

       RW

           Command

    Read /Write

     6

         E

           Command

         Enable

     7

        D0

         Input/Output

      Data(LSB)

     8

        D1

         Input/Output

      Data

     9

        D2

         Input/Output

      Data

    10

        D3

         Input/Output

      Data

    11

        D4

         Input/Output

      Data

    12

        D5

         Input/Output

      Data

    13

        D6

         Input/Output

      Data

    14

        D7

         Input/Output

      Data(MSB)

    15

           A

           LED BKL

          +5v

    16

           K

           LED BKL

       Ground

 Pin Description

Power supply

The first two pins of LCD must be connected to +5v and 0v.

Vo

The Vo pin is a contrast pin which is used to control the contrast of LCD. That is done by variable resistor. In FPGA kit the 10K variable resistor is used to control the contrast. The simple connection is given below Fig 2. There are three pins the two pins are connected to power supply and middle one is connected to Vo.  

Note: The contrast range must be (0- 5v) for proper condition.

 Circuit connection for contrast pin                                                       

Fig 2: Circuit connection for contrast pin

 RS (Register Select)

RS is a command pin for LCD. The LCD command and RW operations are determined by RS pin. The LCD contains two register which is the data and command register. When command writes on the LCD, the data register is used. When the data either read or write on the LCD, the command register is used. The selections of register are determined by the logic status of RS.

 If the logic state of RS is ‘1’, the data register is selected. If the logic state of RS is ‘0’, the command register is selected.    

 Enable

When the data send to data pins of LCD, the high to low pulse will be given.

 Data pins (D0-D1)

The D0-D1 is data I/O pins. The LCD is accepted the 8 bit data as a parallel form. The format of data stream is first bit must be LSB bit continue it the other bits are sent.

Note: The LCD support only ASCII value of whatever the data is.

 LED backlight

The pin no’s 15 & 16 are allocated for LCD backlight. The supply of LED backlight is +5v & 0v. It makes brightness of LCD display. The LED backlight pins denoted as (Anode (A), Cathode (K)) on LCD.   

 Interfacing with Spartan6 FPGA Project Kit

Fig 3: Interfacing Spartan 6 FPGA project Board

LCD Connector Placement on Spartan6 FPGA Project

LCD Connector Placement on Spartan 6 FPGA project Board

LCD consist of 8- Data lines D0-D7, RS- Register Select line, RW-Read Write line, En- Enable line.

 First we need to send commands to initialize the display, Curser Position, Clear Display, increment curser etc. All this command are send to instruction Register. Instruction Register can be enabled by RS = ‘0’, RW = ‘1’, En= ‘1’.

 ASCI Values for Commands used in the code

38 = Function Set: 8-bit, 2 Line, 5x7 Dots

0c = Display on Cursor off

06 = Entry Mode

01= Clear Display

C0 = Place Curser to 2nd line

 

After sending commands, Data can be transferred to Display in the LCD. For sending Data enable Data Register by sending RS= ’1’, RW= ‘1’, En= ’1’.

Data can be transferred in 2 ways 8-bit mode and 4-bit mode. Here we are interfacing in 8-bit mode with the entire Data pin D0-D7.

 

ASCI Values for Data’s used in the code

50 - P   41- A    4e- N   54- T    45- E    43- C    48- H

20- Space 

53- S    4f- O    4c- L    55- U   54- T    49- I     4f- O    4e- N   53- S

VHDL Code consists for 2 counters i and j. i counter used to divide the clock and j counter used to get the array elements.

VHDL Code for 2x16 LCD Display 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

 

entity lcd is

port ( clk    : in std_logic;                          --clock i/p

       lcd_rw : out std_logic;                         --read & write control

       lcd_e : out std_logic;                         --enable control

       lcd_rs : out std_logic;                         --data or command control

       data  : out std_logic_vector(7 downto 0));     --data line

end lcd;
architecture Behavioral of lcd is constant N: integer :=22; type arr is array (1 to N) of std_logic_vector(7 downto 0); constant datas : arr := (X"38",X"0c",X"06",X"01",X"C0",X"50",x"41",x"4e",x"54",x"45",x"43",x"48",x"20",x"53",x"4f",x"4c",x"55",x"54",x"49",x"4f",x"4e",X"53"); --command and data to display

begin

lcd_rw <= '0';  --lcd write

process(clk)

variable i : integer := 0;

variable j : integer := 1;

begin

 

if clk'event and clk = '1' then

if i <= 1000000 then

i := i + 1;

lcd_e <= '1';

data <= datas(j)(7 downto 0);

elsif i > 1000000 and i < 2000000 then

i := i + 1;

lcd_e <= '0';

elsif i = 2000000 then

j := j + 1;

i := 0;

end if;

if j <= 5  then

lcd_rs <= '0';    --command signal

elsif j > 5   then

lcd_rs <= '1';   --data signal

end if;

if j = 22 then  --repeated display of data

j := 5;

end if;

end if;

 

end process;

end Behavioral;

User Constraint File

NET "data[2]" LOC = P17;

NET "data[3]" LOC = P16;

NET "data[4]" LOC = P15;

NET "data[5]" LOC = P14;

NET "data[6]" LOC = P12;

NET "data[7]" LOC = P11;

NET "lcd_e" LOC = P10;

NET "lcd_rs" LOC = P9;

NET "lcd_rw" LOC = P8;

 Output of LCD display

Fig4: Output of LCD display

Pushbutton interface with LCD

The push button is connected to LCD and control by FPGA.

According to code the push button status are displayed on LCD. Initially the LCD displays ‘NO INPUT’. In this code we assigned two push buttons. When press the push button, the LCD showed which button is press either push button 1 or 2.

 

VHDL Code for Push Button to LCD Interface

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is
port ( clk 	: in std_logic;    				--clock i/p
       lcd_rw	: out std_logic;   				--read & write control
	lcd_e 	: out std_logic;   				--enable control
	lcd_rs	: out std_logic;   				--data or command control
	data  	: out std_logic_vector(7 downto 0));   	--data line
end lcd;

architecture Behavioral of lcd is
constant N: integer :=22; 
type arr is array (1 to N) of std_logic_vector(7 downto 0); 
constant datas : arr :=    (X"38",X"0c",X"06",X"01",X"C0",X"50",x"41",x"4e",x"54",x"45",x"43",x"48",x"20",x"53",x"4f",x"4c",x"55",x"54",x"49",x"4f",x"4e",X"53"); --command and data to display                                              

begin
lcd_rw <= '0';  --lcd write
process(clk)
variable i : integer := 0;
variable j : integer := 1;
begin

if clk'event and clk = '1' then
if i <= 1000000 then
i := i + 1;
lcd_e <= '1';
data <= datas(j)(7 downto 0);
elsif i > 1000000 and i < 2000000 then
i := i + 1;
lcd_e <= '0';
elsif i = 2000000 then
j := j + 1;
i := 0;
end if;
if j <= 5  then
lcd_rs <= '0';    --command signal
elsif j > 5   then
lcd_rs <= '1';   --data signal
end if;
if j = 22 then  --repeated display of data
j := 5;
end if;
end if;

end process;
end Behavioral;

 

User Constraint File

NET "clk" LOC = P85;
NET "data[0]" LOC = P22;
NET "data[1]" LOC = P21;
NET "data[2]" LOC = P17;
NET "data[3]" LOC = P16;
NET "data[4]" LOC = P15;
NET "data[5]" LOC = P14;
NET "data[6]" LOC = P12;
NET "data[7]" LOC = P11;
NET "lcd_e" LOC = P10;
NET "lcd_rs" LOC = P9;
NET "lcd_rw" LOC = P8;

Output of LCD

Fig 5: Output of LCD