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Abstract

This design accomplished Tic-Tac-Toe game on Spartan3 FPGA Image Processing kit in VHDL. Firstly, designing the circuits and wiring on experiment board. Secondly, designing the algorithm and programming it in VHDL. Thirdly, synthesizing it in Xilinx Synthesis tool and then implementing it in Xilinx ISE developing suite. Finally download it onto FPGA to run it. This design allows two players to play Tic-Tac-Toe game on the experiment board. The user plays the game from the keyboard. He uses the arrows to move a square on a 3x3 grid on the VGA display. The Xs and 0s are placed by pressing the space bar. The user can move a switch to choose the game mode. He can play against another player or alone against the design. When playing alone, after a X is placed the position of the 0 is returned but not yet shown on the display. Only after another key is pressed the 0 appears on the grid. When the game ends (X or 0 wins or draw game) the marks are automatically erased from the grid and the score is incremented on the seven-segment LED display.

Demonstration Video

 

Tool required

Software:

⇛Xilinx ISE 11.1i

Language:

⇛VHDL

Hardware:

Spartan3 FPGA Image Processing kit

⇛VGA Monitor

⇛PS/2 Keyboard

Block Diagram for TIC TAC TOE using Spartan3 FPGA Image Processing kit

Introduction

Tic-Tac-Toe was tested on Spartan3 FPGA Image Processing kit with a PS2 keyboard and a VGA display. The design of the Tic-Tac-Toe circuit is quite simple. It has 4 inputs and 7 outputs. CLK is the system clock. The keyboard uses a two-wire serial bus including clock and data (KC and KD) to communicate with the host device. Then there is the selection SEL which is connected to a switch from the board. It selects between tow playing modes: player1 vs. player2 or player vs. the board. If player vs. board is selected the circuit picks the next move.

The outputs go to the VGA display and the seven-segment LED display of the board. The board contains a modular 4-digit, common anode seven-segment LED display. In a common anode display, the seven cathodes of the LEDs forming each digit are connected to four common circuit nodes labelled AN0 through AN3. The cathodes of similar segments on all four displays are also connected together into seven common circuit nodes labelled SSEG0 through SSEG6. The five standard VGA signals Red (RED), Green (GRN), Blue (BLU), Horizontal Sync (HS), and Vertical Sync (VS) are routed directly to the VGA connector.



Signal Mode Description

CLK Clock input Main clock input
KD PS2 data input The keyboard sends data to the host only when both
&nbsp the data and clock lines are high (or idle).
KC PS2 clock input The keyboard sends data to the host only when both
&nbsp the data and clock lines are high (or idle).
SEL Switch input Selects game mode
AN Output - 7-seg signal Used to put the score on the seven-segment LED display
SSEG Output - 7-seg signal Used to put the score on the seven-segment LED display
RED Output - VGA signal  
GRN Output - VGA signal  
BLU Output - VGA signal  
HS Output - VGA signal  
VS Output - VGA signal  

Hardware implementation of  TIC TAC TOE game using FPGA

 

1)Power connection ,VGA and PS2 connection to the FPGA kit

1)Power connection ,VGA and PS2 connection to the FPGA kit

2)JTAG connection with the FPGA kit.


2)JTAG connection with the FPGA kit.

 

3) VGA output of the TIC TAC TOE game

             3) VGA output of the TIC TAC TOE game

 

 3) VGA output of the TIC TAC TOE game

Source Code

VHDL Code for TIC TAC TOE using Spartan3 FPGA Image Processing kit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is
    Port ( CLK : in std_logic;
    		 R : in std_logic;         
		 G : in std_logic;         
		 B : in std_logic;         
           HBP : in std_logic_vector(9 downto 0);
           HFP : in std_logic_vector(9 downto 0);
           VBP : in std_logic_vector(9 downto 0);
           VFP : in std_logic_vector(9 downto 0);
		 HPIXELS : in std_logic_vector(9 downto 0);
		 VLINES : in std_logic_vector(9 downto 0);
		 CLKDIVID : out std_logic;
    		 HC_OUT : out std_logic_vector(9 downto 0);
		 VC_OUT : out std_logic_vector(9 downto 0);
		 HS : out std_logic;
           VS : out std_logic;
		 VSENABLE : out std_logic;
           RED : out std_logic;
		 GRN : out std_logic;
		 BLU : out std_logic);
end vga_sync;

architecture Behavioral of vga_sync is

-----------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------
	--These are the Horizontal and Vertical counters
	signal hc, vc			: std_logic_vector(9 downto 0):="0000000000";
	--Clock divider
	signal clkdiv			: std_logic;
	 --Tells whether or not its ok to display data
	signal vidon			: std_logic;
	--Enable for the Vertical counter;			
	signal vsen			: std_logic:='0'; 

-----------------------------------------------------------------------
-- Module Implementation
-----------------------------------------------------------------------
begin
	-- this cuts the 50Mhz clock in half
	process(clk)
		begin
			if(clk = '1' and clk'EVENT) then
				clkdiv <= not clkdiv;
			end if;
		end process;																			
	 clkdivid <= clkdiv;
	
	-- runs the horizontal counter
	process(clkdiv)
		begin
			if(clkdiv = '1' and clkdiv'EVENT) then
				if hc = hpixels then -- if the counter has reached 
								 -- the end of pixel count
					hc <= "0000000000";	 --reset the counter
					vsen <= '1'; -- enable the vertical counter 
							   -- to increment
				else
					hc <= hc + 1; -- increment the horizontal 
							    -- counter
					vsen <= '0';  -- leave the vsenable off
				end if;
		end if;
	end process;
	
	hc_out <= hc;
	-- horizontal sync 
	hs <= '1' when hc(9 downto 7) = "000" else '0'; 
	vsenable <= vsen;
	
	process(clkdiv)
	begin
		-- increment when enabled
		if(clkdiv = '1' and clkdiv'EVENT and vsen = '1') then 
			if vc = vlines then	 	-- reset when the number 
				vc <= "0000000000";	-- of lines is reached
			else 
				vc <= vc + 1; -- increment the vertical counter
			end if;
		end if;
	end process;

	vc_out <= vc;
	-- vertical sync pulse
	vs <= '1' when vc(9 downto 1) = "000000000" else '0'; 
	
	red <= R;
	grn <= G;
	blu <= B;	 

end Behavioral;

Keyboard Interface:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity keyboardVhdl is
	Port ( CLK : in std_logic;
		  KD  : in std_logic;
		  KC  : in std_logic;
		  RDY : buffer std_logic;
	  	  SCANCODE : out std_logic_vector (7 downto 0));
end keyboardVhdl;


architecture Behavioral of keyboardVhdl is

-----------------------------------------------------------------------
-- Signal Declarations
-----------------------------------------------------------------------
	signal clkDiv : std_logic_vector (3 downto 0);
	signal pclk : std_logic;
	signal MUXOUT: std_logic_vector (3 downto 0);
	signal KDI, KCI : std_logic;
	signal DFF1, DFF2 : std_logic;
	signal shiftRegSig1: std_logic_vector (10 downto 0);
	signal shiftRegSig2: std_logic_vector (10 downto 1);
	signal WaitReg: std_logic_vector (7 downto 0) := "00000000";
	signal lastvalue : std_logic_vector(7 downto 0) := "00000000";
	signal receivedChar : std_logic := '0';

-----------------------------------------------------------------------
-- Module Implementation
-----------------------------------------------------------------------
begin
	-- divide the master clock down to a lower frequency
	process (CLK)
	begin
		if (CLK = '1' and CLK'Event) then 
			clkDiv <= clkDiv +1; 
		end if;	
	end Process;

	
	pclk <= clkDiv(3);

	-- flip flops used to condition siglans coming from PS2
	process (pclk, KC, KD)
	begin
		if (pclk = '1' and pclk'Event) then
			DFF1 <= KD; 
			KDI <= DFF1; 
			DFF2 <= KC; 
			KCI <= DFF2;
		end if;
	end process;

	-- shift registers used to clock in scan codes from PS2
	process(KDI, KCI) 
	begin																					  
		if (KCI = '0' and KCI'Event) then
			ShiftRegSig1(10 downto 0) 
				<= KDI & ShiftRegSig1(10 downto 1);
			ShiftRegSig2(10 downto 1) 
				<= ShiftRegSig1(0) & ShiftRegSig2(10 downto 2);
		end if;
	end process;

	--wait register
	process(ShiftRegSig1, ShiftRegSig2, RDY, KCI)
	begin
		if(RDY='1')then 
		  -- reset WaitReg and receivedchar flag 
		  -- after RDY='1' for 1 period
			WaitReg <= "00000000";
			receivedchar <= '0';
		else
			if(KCI'event and KCI = '1')then 
				if (ShiftRegSig2(8 downto 1) = "11110000") then
					WaitReg <= ShiftRegSig1(8 downto 1);
					receivedchar <= '1';
				end if;			
			end if;			
		end if;
	end Process;

	-- saves last read scan code and sets RDY
	process(clk)
	begin
		if(clk'event and clk='1') then
			if (receivedchar='1') then
				lastvalue <= WaitReg;
				RDY <= '1';				
			else
				RDY <= '0';
			end if;
		end if;
	end process;

	scancode <= lastvalue;
				
end Behavioral; 

User Constraint File for TIC TAC TOE VHDL Code

NET "AN"  LOC = "p76"  ;
NET "AN"  LOC = "p77"  ;
NET "BLU"  LOC = "p97"  ;
NET "CLK"  LOC = "p55"  ;
NET "GRN"  LOC = "p96"  ;
NET "HS"  LOC = "p93"  ;
NET "KC"  LOC = "p74"  ;
NET "KD"  LOC = "p73"  ;
NET "RED"  LOC = "p95"  ;
NET "SEL"  LOC = "p99"  ;
NET "SSEG"  LOC = "p82"  ;
NET "SSEG"  LOC = "p83"  ;
NET "SSEG"  LOC = "p84"  ;
NET "SSEG"  LOC = "p85"  ;
NET "SSEG"  LOC = "p86"  ;
NET "SSEG"  LOC = "p87"  ;
NET "SSEG"  LOC = "p89"  ;
NET "VS"  LOC = "p92"  ;

Conclusion

TIC TAC TOE Game was successfully implemented in Spartan3 FPGA Image Processing kit with PS/2 keyboard and VGA monitor interface.