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Abstract

This Project implements the design of graphic game named “Ping Pong” in Spartan3 FPGA Image Processing kit. “Ping Pong” is a game with 2 players. One is the human player and the opponent is created by the game and tries to simulate a basic AI player. The opponent and also the human player are fighting for points. The player controls a green rectangular board and the artificial opponent controls a blue rectangular board. The ball is a small red square that bounce from one board to another and also from the left and right walls. The background of the game is white. The losing occurs when a player isn’t able to catch the ball and the ball passes by him, and so the other player gains a point. This happenes until one player reaches the score of 128 points and then the player remains at this score. The design is complete, meets most of the requirements, and it has been verified by physical implementation.

Demonstration Video

 

Tool required

Software

  • Xilinx ISE 11.1i

Language

  • VHDL

Hardware

Block Diagram for PING PONG Game using Spartan3 FPGA Image Processing kit


Block Diagram for PING PONG Game using Spartan3 FPGA Image Processing kit

Introduction

In the implementation of this game it was used VHDL codes that implements a keyboard reader for the control of the game, a monitor horizontal, vertical synchronizing signals and color signal, a 7 segment 4 digit led display control.

The player controls the game from the key Left Arrow, Right Arrow of the keyboard and also from BTN1 and BTN2 of the DIO4. The game is turned on/off by the SW1.The score of the player and his artificial opponent is shown on a 2 digit 7 segments display.

  • The game inputs and outputs signals are shown in Table 1

Input signals Output signals

Clk-a 50 Mhz clock from the FPGA, synchronous signal Hsync-a synchronous signal used for the horizontal
synchronization of the monitor
SW1-a asynchronous signal generated by the SW1 that
begins or stops the game.
Vsync- a synchronous signal used for the vertical
synchronization of the monitor
BT1- a asynchronous signal generated by BTN1 that
controls the right movement of players pad
 Red, Green, Blue- asynchronous signals used for coloring
 the pixels of the monitor screen.
BT2- a asynchronous signal generated by BTN2 that
controls the left movement of players pad
SSG(6:0)- asynchronous signals used for the 4 digit display,
by turning on/off the segments
PS2C-a synchronous signal that is generated by
the PS/2 keyboard, and contains the clock generated by the keyboard.
AN(1:0)- synchronous signals used for turning on/off
the 2 digit display i.e selecting the corresponding digit
PS2D-a asynchronous signal that is generated by
the PS/2 keyboard, and contain the data from the keyboard
PERR- asynchronous signals that turns on LED1 when
a parity error from reading the keyboard keys appears
RESET-a asynchronous signal that is generated by
the BTN5 and that resets the keyboard reading
mechanism when an error in reading occurs
 FERR- asynchronous signals that turns on LED2 when a
 frame error from reading the keyboard keys appears

 

The player’s and enemy pads are rectangular shapes with 140 column pixels and 20 row pixels. The enemy’s pad slides from left to right or right to left in the top of the screen the first 20 row pixels, but the player’s pad slides in the last 20 row pixels (figure 2).

20 row pixels

Hardware implementation of  Ping Pong game using FPGA

 

1)Power connection ,VGA and PS2 connection to the FPGA kit

                      1)Power connection ,VGA and PS2 connection to the FPGA kit

2)JTAG connection with the FPGA kit.

                      2)JTAG connection with the FPGA kit.

3) VGA output of the Ping Pong game

                                     3) VGA output of the Ping Pong game

 

                   3) VGA output of the Ping Pong game

Source Code

VHDL Code for PING PONG Game using Spartan3 FPGA Image Processing kit

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity vga_sync is port ( clk : in std_logic; 
-- a 50 MHZ CLK hsync : out std_logic;
--Vertical and horizontal syncronizing signals vsync : out std_logic; 
rgb_in: in std_logic_vector(2 downto 0); --3 bit signal for color r, g, b: out std_logic; --Color signal column_out : out std_logic_vector(9 downto 0);
--Column and row position of the pixel generated row_out : out std_logic_vector (9 downto 0));
end vga_sync; architecture vga_sync_arch of vga_sync is signal hcount : integer range 0 to 1023; 
signal vcount : integer range 0 to 1023; 
signal hsync_int : std_logic;
signal en_cnt_v: std_logic;
begin count_h:process (clk, hcount) begin --the columns are countered and hsync is generated if ( clk'event and clk='1') then if hcount=800 then hcount<=0; 
hsync_int<='1';
en_cnt_v<='1';
elsif hcount >,br/>703 then hcount <= hcount+1;
hsync_int<='0'; 
en_cnt_v<='0'; else hcount<=hcount+1; hsync_int<='1';en_cnt_v<='0';
end if; end if;
end process count_h;
hsync<=hsync_int;
count_v: process(clk, hsync_int, vcount)-- the row is countered and vsync is generated begin if ( clk'event and clk='1') then if en_cnt_v='1' then if vcount=521 then vcount<=0;
vsync<='1';
elsif vcount > 518 then vcount <= vcount+1; vsync<='0';
else vcount<=vcount+1;
vsync<='1';
end if; end if; end if;
end process count_v;
-- concurrently assigning column_out and row_out column_out<="0000000000" when hcount -- if the counters are outside of
the displayed area begin if (hcount<48) or (hcount>688) or (vcount<29) or (vcount>509) then r<='0';
g<='0';
b<='0';
else r<=rgb_in(2);
g<=rgb_in(1);
b<=rgb_in(0); end if; 
end process turnoff;
end vga_sync_arch;

User Constraint File for Ping Pong VHDL Code

NET "an" LOC = "P77"; NET "an" LOC = "P76";
NET "ssg" LOC = "P82";
NET "ssg" LOC = "P83";
NET "ssg" LOC = "P84";
NET "ssg" LOC = "P85";
NET "ssg" LOC = "P86";
NET "ssg" LOC = "P87";
NET "ssg" LOC = "P89";
NET "clk" LOC ="P55";
NET "vsync" LOC="P92";
NET "hsync" LOC="P93";
NET "red" LOC="P95";
NET "green" LOC="P96";
NET "blue" LOC="P97";
NET "sw1" LOC="P99";
NET "bt1" LOC="P68";
NET "bt2" LOC="P69";
NET "PS2D" LOC="P73";
NET "PS2C" LOC="P74";
NET "RESET" LOC = "P70";
#---ps2 reset btn5 NET "FERR" LOC = "P82";
#led 1 NET "PERR" LOC = "P83";
#led 2

Conclusion

The game is fully functional as is intended in this form but one’s cane modify from the type of players: can be human to human or AI to AI, or to implement more mode of play, or to implement more speed levels, or to change the position of the board from left to right, to have more player, and so on in Spartan3 FPGA Image Processing kit.