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Abstract

This project implements Temperature monitoring system for Agricultural field using Spartan3an FPGA Starter kit. The most important factors for the quality and productivity of plant growth are temperature and humidity. Continuous monitoring of these environmental variables gives information to the grower to better understand, how each factor affects growth and how to manage maximal crop productiveness .The optimal greenhouse climate adjustment can enable us to improve productivity and to achieve remarkable energy savings - especially during the winter in northern countries. The system itself was usually simple without opportunities to control locally heating, lights, ventilation or some other activity, which was affecting the greenhouse interior climate. For the implementation of agricultural technologies, low cost and real time remote monitoring are needed, in this sense, programmable Logic Devices (PLDs) present as a good option for the technology development and implementation.

Demonstration Video

 

Tool required

Software:

⇛Xilinx ISE 10.1i or above

Language:

⇛VHDL

Hardware:

Spartan3an Starter kit

⇛Zigbee Module

⇛JTAG Cable

Block Diagram for Wireless Temperature Monitoring system using Spartan3an Starter kit

System board:





Control unit:





Introduction

The system comprises of

⇛Sensors

⇛Analog to Digital Converter

Spartan3an FPGA

When any of the above mentioned climatic parameters cross a safety threshold which has to be maintained to protect the crops, the sensors sense the change and the fpga reads this from the data at its input ports after being converted to a digital form by the ADC. The fpga then performs the needed actions by employing relays until the strayed-out parameter has been brought back to its optimum level. Since a fpga is used as the heart of the system, it makes the set-up low-cost and effective nevertheless.

Methodology

To implement a real time monitoring system for agricultural field low cost is a significant factor. In that sense programmable logic device(PLD) is a good option for the technology development and implementation, because PLD’s allow fast development of prototype and the design of complex hardware system using FPGA’S and commercial PLD’s.

Environmental parameters:

a) Temperature

Temperature for plant (flowers or vegetables) growth required is Day temperature around 26degreeC to 30degreeC Night temperature around 15 degree C to 18 degree C This temperature can be controlled using ventilation or fan pad cooling systems.

b) Humidity

For floriculture 70% to 80% humidity should be maintained and for vegetables 60% to 70% humidity is required. Humidifiers or foggers are used to maintain this humidity range.

This project is divided into three phases:

  • Identifying the appropriate sensor for measuring temperature and relative humidity. Temperature sensor to be used is RTD so that low cost aim can be successful with best stability.
  • Design of controller using FPGA, sensor interface card, isolation circuit for input and output, output relay card.
  • Development of a user interface software.



LM35

The LM35 series are precision integrated-circuit temperature sensors, whose output voltage is linearly proportional to the Celsius (Centigrade) temperature. The LM35 thus has an advantage over linear temperature sensors calibrated in ° Kelvin, as the user is not required to subtract a large constant voltage from its output to obtain convenient Centigrade scaling.

Wireless Temperature Output Image

 Wireless Temperature Output Image

 

Wireless Temperature Output Image

 

Wireless Temperature Output Image

 

Wireless Temperature Output Image

 

Source Code

VHDL Code for Temperature Monitoring System using Spartan3an Starter kit

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
entity adc_ch0 is
port ( clk   : in std_logic;
           led : out std_logic_vector(7 downto 0);
       cs    : out std_logic;
           sc  : out std_logic;
           do    : out std_logic;
           dout    : out std_logic;
           din   : in std_logic);
end adc_ch0;
 
architecture Behavioral of adc_ch0 is
type state is (spi,conversion,transmission);
signal presentstate : state := spi;
signal f : std_logic;
type arr is array (0 to 12) of std_logic_vector(9 downto 0);
signal store : arr;
begin
 
process(clk)
variable i,j,k : integer := 0;
variable tot : std_logic_vector(11 downto 0) := "000000000000";
begin
 
if clk'event and clk = '1' then
if presentstate = spi then
     if i <= 50 then  
          i := i + 1;
          sc <= '1';
     elsif i > 50 and i < 100 then     
          i := i + 1;
          sc <= '0';
     elsif i = 100 then   
          i := 0;   
          if j < 18 then
              j := j + 1;
          elsif j = 18 then
              presentstate <= conversion;
              j := 0;
          end if;
     end if;
    
     if j = 0 or j >= 18 then
          cs <= '1';
     else
          cs <= '0';
     end if;
    
     if i > 40 and i < 60 then
          case j is
              when 0 => do <= '0';
              when 1 => do <= '1';
              when 2 => do <= '1';
              when 3 => do <= '1';          -----channel bit
              when 4 => do <= '1';
              when others => null;
          end case;
     end if;
    
     if i >= 0 and i < 10 then
          case j is
              when 6 => tot(11) := din;
              when 7 => tot(10) := din;
              when 8 => tot(9) := din;
              when 9 => tot(8) := din;
              when 10 => tot(7) := din;
              when 11 => tot(6) := din;
              when 12 => tot(5) := din;
              when 13 => tot(4) := din;
              when 14 => tot(3) := din;
              when 15 => tot(2) := din;
              when 16 => tot(1) := din;
              when 17 => tot(0) := din;
              when others => null;
          end case;
     end if;
end if;
--------------------------------------------------------------
if presentstate = conversion then
     cs <= '1';
     led(0) <= tot(9);
     led(1) <= tot(8);
     led(2) <= tot(7);
     led(3) <= tot(6);
     led(4) <= tot(5);
     led(5) <= tot(4);
     led(6) <= tot(3);
     led(7) <= tot(2);
    
store(0) <= "1010101000";--T
store(1) <= "1010001010";--E
store(2) <= "1010011010";--M
store(3) <= "1001000000";--SPACE
 
if tot(9 downto 2) >=  "00000000"  and tot(9 downto 2) <= "00010100"  then
store(4)  <= "1010011000";
store(5) <= "1010011110";                               --Lo
elsif tot(9 downto 2) >  "00010100"  and tot(9 downto 2) <= "00010111"  then
store(4)  <= "1001100010";
store(5) <= "1001101000";                               --16
elsif tot(9 downto 2) >  "00010111"  and tot(9 downto 2) <= "00011010"  then
store(4)  <= "1001100010";
store(5) <= "1001110000";                               --18
elsif tot(9 downto 2) >  "00011010"  and tot(9 downto 2) <= "00011010"  then
store(4)  <= "1001100100";
store(5) <= "1001100000";                               --20
elsif tot(9 downto 2) >  "00011101"  and tot(9 downto 2) <= "00100000"  then
store(4)  <= "1001100100";
store(5) <= "1001100100";                               --22
elsif tot(9 downto 2) >  "00100000"  and tot(9 downto 2) <= "00100011"  then
store(4)  <= "1001100100";
store(5) <= "1001101000";                               --24
elsif tot(9 downto 2) >  "00100011"  and tot(9 downto 2) <= "00100110"  then
store(4)  <= "1001100100";
store(5) <= "1001101100";                               --26
elsif tot(9 downto 2) >  "00100110"  and tot(9 downto 2) <= "00101010"  then
store(4)  <= "1001100100";
store(5) <= "1001110000";                               --28
elsif tot(9 downto 2) >  "00101010"  and tot(9 downto 2) <= "00101110"  then
store(4)  <= "1001100110";
store(5) <= "1001100000";                               --30
elsif tot(9 downto 2) >  "00101110"  and tot(9 downto 2) <= "00110010"  then
store(4)  <= "1001100110";
store(5) <= "1001100100";                               --32
elsif tot(9 downto 2) >  "00110010"  and tot(9 downto 2) <= "00110101"  then
store(4)  <= "1001100110";
store(5) <= "1001101000";                               --34
elsif tot(9 downto 2) >  "00110101"  and tot(9 downto 2) <= "00111000"  then
store(4)  <= "1001100110";
store(5) <= "1001101100";                               --36
elsif tot(9 downto 2) >  "00111000"  and tot(9 downto 2) <= "00111011" then
store(4)  <= "1001100110";
store(5) <= "1001110000";                               --38
elsif tot(9 downto 2) >  "00111011"  and tot(9 downto 2) <=  "00111110" then
store(4)  <= "1001101000";
store(5) <= "1001100000";                               --40
elsif tot(9 downto 2) >  "00111110" and tot(9 downto 2) <= "01000001" then
store(4)  <= "1001101000";
store(5) <= "1001100100";                               --42
elsif tot(9 downto 2) >  "01000001"  and tot(9 downto 2) <= "01000100"  then           
store(4)  <= "1001101000";
store(5) <= "1001101000";                               --44
elsif tot(9 downto 2) >  "01000100"  and tot(9 downto 2) <= "01000111"  then
store(4)  <= "1001101000";
store(5) <= "1001101100";                               --46
elsif tot(9 downto 2) >  "01010000"  and tot(9 downto 2) <= "01010101"  then
store(4)  <= "1001101000";
store(5) <= "1001110000";                               --48
elsif tot(9 downto 2) >  "01010101"  and tot(9 downto 2) <= "11111111"  then
store(4)  <= "1010010000";
store(5) <= "1010010010";                               --50 Hi
end if;
store(6) <=  "1000011010";
 
     if i < 50000 then
          i := i + 1;
     elsif i = 50000 then  
          i := 0;   
          presentstate <= transmission;
     end if;
end if;
--------------------------------------------------------------
if presentstate = transmission then 
     cs <= '1';
     if i < 5209 then 
          i := i + 1 ; 
          dout <= store(k)(j);
     elsif i = 5209 then 
          if j < 9 then
              j := j + 1;
          elsif j = 9 then
              j := 0 ;
              if k < 6 then
                   k := k + 1;
              elsif k = 6 then
                   presentstate <= spi;
                   k := 0;
              end if;
          end if;
          i := 0; 
     end if;
end if;
end if;
end process;                                        
  end Behavioral;

User Constraint file for Temperature Monitoring VHDL Code

NET "clk" LOC = P57; NET "cs" LOC = P110; NET "din" LOC = P114; 
NET "do" LOC = P113; NET "dout" LOC = P3; NET "sc" LOC = P111; 

Conclusion

Digital Temperature controller which can make a Agricultural environment automated using Spartan3an Project Kit... People can control their electrical devices via Digital Temperature controller and set up the controlling actions in the computer. We think this product have high potential for marketing in the future.