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Abstract

In this project proposed a kind of parallel processing construction of Sobel edge detection enhancement algorithm, which can quickly get the result of one pixel in only one clock periods. The algorithm is designed with a FPGA chip called XC3S200- 4tq144, and it can process 128×128×8 Gray Scale Image successfully. Sobel operator is chosen due to its property of less deterioration in high levels of noise. The design can locate the edge of the gray image quickly and efficiently. Experiment is carried out in MATLAB and on FPGA board.

Demonstration Video

 

Tool required

Software:

⇛Xilinx ISE 10.1i or above

⇛Xilinx EDK 10.1i or above

⇛VB GUI to display output

Language:

⇛VHDL, System C

Hardware:

Spartan3 EDK FPGA kit

⇛JTAG Cable

⇛PC

⇛Serial Cable

Edge Detection Representation

Representation_Edge_Detection

Block Diagram for FPGA Based Sobal Edge Detection using Spartan3 FPGA Project Kit



Blg_dgm_Edge_DetectionIntroduction:

The Sobel operator is used in image processing, particularly within edge detection algorithms. Technically, it is a discrete differentiation operator, computing an approximation of the gradient of the image intensity function. At each point in the image, the result of the Sobel operator is either the corresponding gradient vector or the norm of this vector. The Sobel operator is based on convolving the image with a small, separable, and integer valued filter in horizontal and vertical direction and is therefore relatively inexpensive in terms of computations. On the other hand, the gradient approximation that it produces is relatively crude, in particular for high frequency variations in the image.

The Sobel Edge Detector uses a simple convolution kernel to create a series of gradient magnitudes. For those you of mathematically inclined, applying convolution K to pixel group p can be represented as:


Edge_Detection_formula

Approximates the gradient by using a row and a column mask, which will approximate the first derivative in each direction. The Sobel edge detection mask look for edge in both the horizontal and vertical directions, and then combine this information into a single metric.

Edge_Detection_Matrx

These mask are each convolved with the image. At each pixel location we now have two numbers: s1, corresponding to the result from the vertical edge mask, and s2, from the horizontal edge mask. We use the number to compute two metrics, the edge magnitude and the edge direction, defined as follows:

Edge_Detection_Fm_mag_dr

 

Hardware implementation of Edge detection using FPGA

 

1) Power connection, serial(RS232) connection and JTAG Connection to the FPGA kit


                                  1) Power connection, serial(RS232) connection and JTAG Connection to the FPGA kit                                                        

2)JTAG connection with the FPGA kit.

                                                 2)JTAG connection with the FPGA kit.

3) Edge detected output transmitted serial to a PC and visualized using a VB GUI

                                              3) Edge detected output transmitted serial to a PC and visualized using a VB GUI

Sobal Edge Output Image

                Sobal Edge Output Image

 

Sobal Edge Output Image

 

Sobal Edge Output Image

 

Sobal Edge Output Image

 

Sobal Edge Output Image

Source Code

C Code Noise Removal Median Filter Using Spartan3 FPGA Image Processing Kit

#include "stdio.h"
#include "math.h"
#include 
int kernel_hr[3][3];
int kernel_vr[3][3];
int INPUT[128][128];
int output1[128][128];
int output2[128][128];
int Sliding_window_hr[3][3];
int Sliding_window_vr[3][3];

void main()
{
int i,j;
int len=127;
kernel_hr[0][0] = -1; kernel_hr[0][1] = 0; kernel_hr[0][2] = 1;
kernel_hr[1][0] = -2; kernel_hr[1][1] = 0; kernel_hr[1][2] = 2;
kernel_hr[2][0] = -1; kernel_hr[2][1] = 0; kernel_hr[2][2] = 1;

kernel_vr[0][0] = -1; kernel_vr[0][1] = -2; kernel_vr[0][2] = -1;
kernel_vr[1][0] =  0; kernel_vr[1][1] =  0; kernel_vr[1][2] =  0;
kernel_vr[2][0] =  1; kernel_vr[2][1] =  2; kernel_vr[2][2] =  1;

for( i=0;i<128;i++)
{
for( j=0;j<128;j++)
{
int a;
	INPUT[i][j]=hai[i][j];
	xil_printf("%d\n",INPUT[i][j]);
}
}

for(i=0;i<128;i++)
{
for (j=0;j<128;j++)
{                      
	if (i==0 & j==0)
	{

	}
  
	else if (i==0 & j==len)
	{
  
	}
	else if (i==len & j==0)
	{
																  
	}
	else if (j==len & i==len)
	{
												  
	}
	else if (i==1)
	{          
  
	}
	else if (i==len)
	{
  
	}
	else if (j==len)
	{
  
	}
	else if (j==1)
	{
				  
	}
	else
	{                                                          
	Sliding_window_hr[1][1]=INPUT[i-1][j-1] * kernel_hr[0][0];                              Sliding_window_hr[1][2]=INPUT[i-1][j]                     *      kernel_hr[0][1];

	Sliding_window_hr[1][3]=INPUT[i-1][j+1] * kernel_hr[0][2];
	Sliding_window_hr[2][1]=INPUT[i][j-1] * kernel_hr[1][0];
	Sliding_window_hr[2][2]=INPUT[i][j] * kernel_hr[1][1];
	Sliding_window_hr[2][3]=INPUT[i][j+1] * kernel_hr[1][2];
	Sliding_window_hr[3][1]=INPUT[i+1][j-1] * kernel_hr[2][0];
	Sliding_window_hr[3][2]=INPUT[i+1][j] * kernel_hr[2][1];
	Sliding_window_hr[3][3]=INPUT[i+1][j+1] * kernel_hr[2][2];

output1[i][j]=Sliding_window_hr[1][1]+Sliding_window_hr[1][2]+Sliding_window_hr[1][3]+Sliding_window_hr[2][1]+Sliding_window_hr[2][2]+Sliding_window_hr[2][3]+Sliding_window_hr[3][1]+Sliding_window_hr[3][2]+Sliding_window_hr[3][3];
  
	Sliding_window_vr[1][1]=INPUT[i-1][j-1] * kernel_vr[0][0];
	Sliding_window_vr[1][2]=INPUT[i-1][j] * kernel_vr[0][1];
	Sliding_window_vr[1][3]=INPUT[i-1][j+1] * kernel_vr[0][2];
	Sliding_window_vr[2][1]=INPUT[i][j-1] * kernel_vr[1][0];
	Sliding_window_vr[2][2]=INPUT[i][j] * kernel_vr[1][1];

	Sliding_window_vr[2][3]=INPUT[i][j+1] * kernel_vr[1][2];
	Sliding_window_vr[3][1]=INPUT[i+1][j-1] * kernel_vr[2][0];
	Sliding_window_vr[3][2]=INPUT[i+1][j] * kernel_vr[2][1];
	Sliding_window_vr[3][3]=INPUT[i+1][j+1] * kernel_vr[2][2];

output2[i][j]=Sliding_window_vr[1][1]+Sliding_window_vr[1][2]+Sliding_window_vr[1][3]+Sliding_window_vr[2][1]+Sliding_window_vr[2][2]+Sliding_window_vr[2][3]+Sliding_window_vr[3][1]+Sliding_window_vr[3][2]+Sliding_window_vr[3][3];
  
	}
}
}

for( i=0;i<128;i++)
{
for( j=0;j<128;j++)
{
	if(output1[i][j]>output2[i][j])
	{
		xil_printf("%d\n",output1[i][j]);
	}
	Else

	{
		xil_printf("%d\n",output2[i][j]);
	}
  
}
}
}

Conclusion

The Sobel operator adding the orientation of the convolution kernels can locate accurately the edge, thin the boundary lines, and not be sensitive to noise. The Spartan3 FPGA Image Processing Kit implementation of it meets the real-time requirements. This architecture based on FPGA is much better than processing images on software platform.